13

AT25DF512C

DS-25DF512C–030A–4/2014

Figure 9-1.

Write Enable

9.2

Write Disable

The Write Disable command is used to reset the Write Enable Latch (WEL) bit in the Status Register to the logical “0”

state. With the WEL bit reset, all Byte/Page Program, erase, Program OTP Security Register, and Write Status Register

commands will not be executed. Other conditions can also cause the WEL bit to be reset; for more details, refer to the

WEL bit section of the Status Register description.

To issue the Write Disable command, the CS pin must first be asserted and the opcode of 04h must be clocked into the

device. No address bytes need to be clocked into the device, and any data clocked in after the opcode will be ignored.

When the CS pin is deasserted, the WEL bit in the Status Register will be reset to a logical “0”. The complete opcode

must be clocked into the device before the CS pin is deasserted, and the CS pin must be deasserted on an even byte

boundary (multiples of eight bits); otherwise, the device will abort the operation and the state of the WEL bit will not

change.

Figure 9-2.

Write Disable

9.3

Block Protection

The device can be software protected against erroneous or malicious program or erase operations by utilizing the Block

Protection feature of the device. Block Protection can be enabled or disabled by using the Write Status Register

command to change the value of the Block Protection (BP0) bit in the Status Register. The following table outlines the

two states of the BP0 bit and the associated protection area

.

SCK

CS

SI

SO

MSB

23

1

0

00000110

67

5

4

OPCODE

HIGH-IMPEDANCE

SCK

CS

SI

SO

MSB

23

1

0

00000100

67

5

4

OPCODE

HIGH-IMPEDANCE

Table 9-1.

Memory Array Protection

Protection Level

BP0

Protected Memory Address

None

0

None

Full Memory

1

00000h - 00FFFFh