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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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46DR16640A датащи(PDF) 21 Page - Integrated Silicon Solution, Inc |
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46DR16640A датащи(HTML) 21 Page - Integrated Silicon Solution, Inc |
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21 / 28 page  IS43/46DR81280A, IS43/46DR16640A Integrated Silicon Solution, Inc. – www.issi.com – 21 Rev. D, 08/30/2011 AC Characteristics (AC Operating Conditions Unless Otherwise Noted) Parameter Symbol ‐37C ‐3D ‐25E ‐25D Units Notes DDR2‐533C DDR2‐667D DDR2‐800E DDR2‐800D Min Max Min Max Min Max Min Max Row Cycle Time tRC 60 60 60 57.5 ns Auto Refresh Row Cycle Time tRFC 127.5 127.5 127.5 127.5 ns 11 Row Active Time tRAS 45 70K 45 70K 45 70K 45 70K ns 21 Row Active to Column Address Delay tRCD 15 15 15 12.5 ns 20 Row Active to Row Active Delay tRRD(x8) 7.5 7.5 7.5 7.5 ns tRRD(x16) 10 10 10 10 ns Four Activate Window tFAW(x8) 37.5 37.5 35 35 ns tFAW(x16) 50 50 45 45 ns Column Address to Column Address Delay tCCD 2 2 2 2 tCK Row Precharge Time tRP 15 15 15 12.5 ns Write Recovery Time tWR 15 15 15 15 ns Auto precharge Write recovery + Precharge Time tDAL Min = tWR+tRP, Max = n/a ns 12 Clock Cycle Time tCK3 (CL=3) 5 8 5 8 ns 2, 24 tCK4 (CL=4) 3.75 8 3.75 8 3.75 8 3.75 8 ns 2, 24 tCK5 (CL=5) 3 8 3 8 2.5 8 ns 2, 24 tCK6 (CL=6) 2.5 8 2.5 8 ns 24 Clock High Level Width tCH 0.45 0.55 0.48 0.52 0.48 0.52 0.48 0.52 tCK Clock Low Level Width tCL 0.45 0.55 0.48 0.52 0.48 0.52 0.48 0.52 tCK Cycle to cycle tJITcc 250 250 200 200 ps Data‐Out Edge to Clock Skew Edge tAC ‐0.5 0.45 ‐0.45 0.45 ‐0.4 0.4 ‐0.4 0.4 ns DQS‐Out Edge to Clock Skew Edge tDQSCK ‐0.45 0.4 ‐0.4 0.4 ‐0.35 0.35 ‐0.35 0.35 ns DQS‐Out Edge to Clock Skew Edge tDQSQ 0.3 0.24 0.2 0.2 ns Data‐Out Hold Time from DQS tQH Min = tHP(min)‐tQHS, Max = n/a ns Data Hold Skew Factor tQHS 400 340 300 300 ps Clock Half Period tHP Min = tCH(min)/tCL(min), Max = n/a ns 5 |
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