MA28151 datasheet(5/22 Pages) DYNEX

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MA28151

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3. PROGRAMMING THE MA28151

3.1 MODE AND COMMAND INSTRUCTIONS

Prior to starting data transmission or reception, the

MA28151 must be loaded with a set of control words

generated by the CPU. These control signals define the

complete functional definition of the MA28151 and must

immediately follow a Reset operation (internal or external).

The control words are split into two formats:

1. Mode Instruction

2. Command Instruction

3.1.1 Mode Instruction

This instruction defines the general operational

characteristics of the MA28151. It must follow a Reset

operation (internal or external). Once the Mode instruction has

been written into the MA28151 by the CPU, SYNC characters

or Command Instructions may be written.

3.1.2 Command Instruction

This instruction defines a word that is used to control the

actual operation of the MA28151.

Both the Mode and Command Instruction must conform to

a specified sequence for proper device operation. The Mode

instruction must be written immediately following a Reset

operation,

prior

using

the

MA28151

for

data

communications.

All control words written into the MA28151 after the Mode

Instruction will load the Command Instruction. Command

Instructions can be written into the MA28151 at any time in the

data block during the operation of the MA28151. To return to

the Mode Instruction format, the master Reset bit in the

Command Instruction word can be set to initiate an internal

Reset operation. This automatically places the MA28151 back

into the Mode Instruction format. Command Instructions must

follow the Mode Instructions or Sync characters.

3.2 MODE INSTRUCTION DEFINITION

The MA28151 can be used for either Asynchronous or

Synchronous data communications. To understand how the

Mode Instruction defines the functional operation of the

MA28151, the designer can best view the device as two

separate components, one Asynchronous and the other

Synchronous, sharing the same package. The format

definition can be changed only after a master chip Reset. For

explanation purposes the two formats will be isolated.

NOTE: When parity is enabled it is not considered as one

of the data bits for the purpose of programming the word

length. The actual parity bit received on the Rx Data line

cannot be read on the Data Bus. In the case of a programmed

character length of less than 8 bits, the least significant data

bus bits will hold the data; unused bits are ‘don’t care’ when

writing data to the MA28151, and will be zeros when reading

the data from the MA28151.

3.3 TEST MODE

The Mode Instruction can be used to select a scan path

test facility. In this mode a test vector is read in through RxD

and read out in TxD. For further information of test mode

please contact GEC Plessey Semiconductors.

3.4 ASYNCHRONOUS MODE (TRANSMISSION)

Whenever a data character is sent by the CPU the

MA28151 automatically adds a Start bit (low level), followed by

the data bits (least significant bit first,) and the programmed

number of Stop bits to each character. Also, an even or odd

Parity bit is inserted prior to the Stop bit(s), as defined by the

Mode Instruction. The Character is then transmitted as a serial

data stream on the TxD output. The serial data is shifted out on

the falling edge of

TxC at a rate equal to 1, 1⁄16 or 1⁄64 times that

of the

TxC, as defined by the Mode Instruction. BREAK

characters can be continuously sent to the TxD if commanded

to do so.

When no data characters have been loaded into the

MA28151 the TxD output remains high (marking) unless a

Break (continuously low) has been programmed.

3.5 ASYNCHRONOUS MODE (RECEIVE)

The RxD line is normally high. A falling edge on this line

triggers the beginning of a START bit. The validity of this

START bit is checked by again strobing this bit at its nominal

center (16x or 64X mode only). If a low is detected again, it is a

valid START bit, and the bit counter will start counting. The bit

counter thus locates the center of the data bits, the parity bit (if

it exists) and the stop bits. If a parity error occurs, the parity

error flag is set. Data and parity bits are sampled on the RxD

pin with the rising edge of

RxC. If a low level is detected as the

STOP bit, the Framing Error flag will be set. The STOP bit

signals the end of a character. Note that the receiver requires

only one stop bit, regardless of the number of stop bits

programmed. This character is then loaded into the parallel l/O

buffer of the MA28151. The RxRDY pin is raised to signal the

CPU that a character is ready to be fetched.

If a previous character has not been fetched by the CPU,

the present character replaces it in the l/O buffer, and the

OVERRUN Error flag is raised (thus the previous character is

lost). All of the error flags can be reset by an Error Reset

Instruction. The occurrence of any of these errors will not affect

the operation of the MA28151.

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