MA28151 datasheet(4/22 Pages) DYNEX

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MA28151

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the Receiver must be enabled and a character must finish

assembly and be transferred to the Data Output Register

Failure to read the received character from the Rx Data

Output Register prior to the assembly of the next Rx Data

character will set overrun condition error and the previous

character will be written over and lost. If the Rx Data is being

read by the CPU when the internal transfer is occurring, the

overrun error will be set and the old character will be Iost.

1.22

RxC (RECEIVER CLOCK)

The Receiver Clock controls the rate at which the character

is to be received. In Synchronous Mode the Baud Rate (1x) is

equal to the actual frequency of

RxC. In Asynchronous Mode,

the Baud Rate is a fraction of the actual

RxC frequency. A

portion of the mode instruction selects this factor: 1,1⁄16 or 1⁄64 of

the Receiver Clock.

For example:

Baud Rate equals 300 Baud, if

RxC equals 300 Hz in the 1 x mode:

RxC equals 4800 Hz in the 16x mode

RxC equals 19.2 KHz in the 64x mode.

Baud Rate equals 2400 Baud if

RxC equals 2400Hz in the 1x mode

RxC equals 38.4 KHz in the 16x mode;

RxC equals 153.6 KHz in the 64x mode.

Data is sampled into the MA28151 on the rising edge of

RxC.

Note: In most communications systems, the MA28151 will

be handling both the transmission and reception operations of

a single link. Consequently the Receive and Transmit Baud

Rates will be the same. Both

TxC and RxC will require identical

frequencies for this operation and can be tied together and

connected to a single frequency source (Baud Rate

Generator) to simplify the interface.

1.23 SYNC/BREAK DETECT (SYNDET/BRKDET)

This pin is used in Synchronous Mode for SYNDET and

may be used as either input or output, programmable through

the Control Word. It is reset to output mode, low upon RESET.

When used as an output (internal Sync mode), the SYNDET

pin will go high to indicate that the MA28151 has located the

SYNC character in the Receive mode. If the MA28151 is

programmed to use double Sync characters (bi-sync), the

SYNDET will go high in the middle of the last bit of the second

Sync character.

SYNDET is automatically reset upon a Status Read

operation.

When used as an input (external SYNC detect mode), a

positive going signal will cause the MA28151 to start

assembling data characters on the rising edge of the next

RxC.

Once in SYNC, the high input signal can be removed. When

External SYNC Detect is programmed, Internal SYNC Detect

is disabled.

1.24 BREAK (ASYNC MODE ONLY)

This output will go high whenever the receiver remains low

through two consecutive stop bit sequences including the start

bits, data bits, and parity bits. Break Detect may also be read

as a Status bit. It is reset only upon a master chip Reset or Rx

Data returning to a “one” state.

C/D

ACTION

MODE INSTRUCTION

SYNC CHARACTER 1 (SYNC ONLY) *

SYNC CHARACTER 2 (SYNC ONLY) *

COMMAND INSTRUCTION

DATA

COMMAND INSTRUCTION

DATA

COMMAND INSTRUCTION

Note: The second sync character is skipped if mode instruction

has programmed the MA28151 to single character mode. Both

sync characters are skipped if mode instruction has

programmed the MA28151 to async mode

Figure 3: Typical data block

2. OPERATION DESCRIPTION

2.1 GENERAL

The complete functional definition of the MA28151 is

programmed by the system’s software. A set of control words

must be sent out by the CPU to initialize the MA28151 to

support the desired communications format. These control

words will program the: Baud Rate, Character Length, Number

of Stop Bits, Synchronous or Asynchronous Operation, Even/

Odd/Off Parity, etc. In the Synchronous Mode, options are also

provided to select either internal or external character

synchronization.

Once programmed, the MA28151 is ready to perform its

communication functions. The TxRDY output is raised high to

signal the CPU that the MA28151 is ready to receive a data

character from the CPU. This output (TxRDY) is reset

automatically when the CPU writes a character into the

MA28151. Alternatively, the MA28151 receives serial data

from the MODEM or l/O device. Upon receiving an entire

character, the RxRDY output is raised high to signal the CPU

that the MA28151 has a complete character ready for the CPU

to fetch. RxRDY is reset automatically upon the CPU data read

operation.

The MA28151 cannot begin transmission until the

TxEnable (Transmitter Enable) bit is set in the Command

instruction and it has received a Clear To Send (

CTS) input.

The TxD output will be held in the marking state upon Reset.

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