DS21372

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1.

GENERAL OPERATION

1.1

PATTERN GENERATION

The DS21372 is programmed to generate a particular test pattern by programming the following registers:

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Pattern Set Registers (PSR)

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Pattern Length Register (PLR)

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Polynomial Tap Register (PTR)

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Pattern Control Register (PCR)

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Error Insertion Register (EIR)

Please see Tables 4 and 5 for examples of how to program these registers in order to generate some

standard test patterns. Once these registers are programmed, the user will then toggle the TL (Transmit

Load) bit or pin to load the pattern into the onboard pattern generation circuitry and the pattern will begin

appearing at the TDATA pin.

1.2

PATTERN SYNCHRONIZATION

The DS21372 expects to receive the same pattern that it transmitted. The synchronizer examines the data

at RDATA and looks for characteristics of the transmitted pattern. The user can control the onboard

synchronizer with the Sync Enable and Resync bits in the Pattern Control Register.

In pseudorandom mode, the received pattern is tested to see if it fits the polynomial generator as defined

in the transmit side. For pseudorandom patterns, only the original pattern and an all ones pattern or an all

0s pattern will satisfy this test. Synchronization in pseudorandom pattern mode should be qualified by

using the RA1 and RA0 indicators in the Status Register. Synchronization is declared after 34 + n bits are

received without error, where n is the exponent in the polynomial from Table 4. Once in synchronization

(SR.0 = 1) any deviation from this pattern will be counted by the Bit Error Count Register.

In repetitive pattern mode a received pattern of the same length as being transmitted will satisfy this test.

Synchronization in repetitive pattern mode should be qualified by using the RA1 and RA0 indicators in

the Status Register and examining the Pattern Receive Register (PRR0--3). See section 10 for an

explanation of the Pattern Receive Register. Once in synchronization (SR.0 = 1) any deviation from this

pattern will be counted by the Bit Error Count Register.

1.3

BER CALCULATION

Users can calculate the actual Bit Error Rate (BER) of the digital communications channel by reading the

bit error count out of the Bit Error Count Register (BECR) and reading the bit count out of the Bit Count

Register (BCR) and then dividing the BECR value with the BCR value. The user has total control over

the integration period of the measurement. The LC (Load Count) bit or pin is used to set the integration

period.

1.4

GENERATING ERRORS

Via the Error Insertion Register (EIR), the user can intentionally inject a particular error rate into the

transmitted data stream. Injecting errors allows users to stress communication links and to check the

functionality of error monitoring equipment along the path.