DS21372

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PATTERN RECEIVE REGISTERS

(MSB)

(LSB)

PR31

PR30

PR29

PR28

PR27

PR26

PR25

PR24

PRR3 (addr.=10 Hex)

PR23

PR22

PR21

PR20

PR19

PR18

PR17

PR16

PRR2 (addr.=11 Hex)

PR15

PR14

PR13

PR12

PR11

PR10

PR9

PR8

PRR1 (addr.=12 Hex)

PR7

PR6

PR5

PR4

PR3

PR2

PR1

PR0

PRR0 (addr.=13 Hex)

11.

STATUS REGISTER AND INTERRUPT MASK REGISTER

The Status Register (SR) contains information on the current real time status of the DS21372. When a

particular event has occurred, the appropriate bit in the register will be set to a 1. All of the bits in these

registers (except for the SYNC bit) operate in a latched fashion. This means that if an event occurs and a

bit is set to a 1 in any of the registers, it will remain set until the user reads that bit. For the BED, BCOF,

and BECOF status bits, they will be cleared when read and will not be set again until the event has

occurred again. For RLOS, RA0, and RA1 status bits, they will be cleared when read if the condition no

longer persists.

and events in the SR can be either masked or unmasked from the interrupt pins via the Interrupt Mask

Register (IMR).

SR: STATUS REGISTER (ADDRESS=14 HEX)

(MSB)

(LSB)

-

RA1

RA0

RLOS

BED

BCOF

BECOF

SYNC

SYMBOL

POSITION

NAME AND DESCRIPTION

-SR.7

Not Assigned. Could be any value when read.

RA1

SR.6

Receive All Ones. Set when 32 consecutive 1s are received;

allowed to be cleared when a 0 is received.

RA0

SR.5

Receive All Zeros. Set when 32 consecutive 0s are received;

allowed to be cleared when a 1 is received.

RLOS

SR.4

Receive Loss Of Sync. Set when the device is searching for

synchronization. Once sync is achieved, will remain set until

read.

BED

SR.3

Bit Error Detection. Set when bit errors are detected.

BCOF

SR.2

Bit Counter Overflow. Set when the 32-bit BCR overflows.

BECOF

SR.1

Bit Error Count Overflow. Set when the 32-bit BECR

overflows.

SYNC

SR.0

Sync. Real time status of the synchronizer (this bit is not

latched). Will be set when synchronization is declared. Will be

cleared when 6 or more bits out of 64 are received in error (if

PCR.2 = 0).