DS1682

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will be able to be written. Once written twice to AAh, the Write Disable to set the Write Disable flag to a

1, it will not be able to be reset and the Configuration register, Total Time Accumulate register, Event

Counter, and Alarm Trip Point register will become Read-Only. The User memory is not affected by the

Write Disable register.

GLITCH CONTROL CIRCUIT

The DS1682 has a built in glitch control circuit to prevent input noise on the EVENT pin from triggering

false events or corrupting the data.

USER MEMORY

There are 10 bytes of user programmable, EEPROM memory. Once the Write Memory Disable Flag is

set to a one, the memory can not be erased or written to again. This is good for locating serial numbers,

manufacture dates, warrantee information, or other important information.

With the Write Memory

Disable Flag set to a 0, the user memory is readable, writable and erasable.

SERIAL INTERFACE

The DS1682 provides two-wire serial communications.

2-WIRE SERIAL DATA BUS

The DS1682 supports a bi-directional two-wire bus and data transmission protocol. A device that sends

data onto the bus is defined as a transmitter, and a device receiving data as a receiver. The device that

controls the message is called a “master”. The devices that are controlled by the master are “slaves”. The

bus must be controlled by a master device which generates the serial clock (SCL), controls the bus access,

and generates the START and STOP conditions. The DS1682 operates as a slave on the two-wire bus.

Connections to the bus are made via the open-drain I/O lines SDA and SCL.

The following bus protocol has been defined (See Figure 2):

Data transfer may be initiated only when the bus is not busy.

During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in

the data line while the clock line is high will be interpreted as control signals.

Accordingly, the following bus conditions have been defined:

Bus not busy: Both data and clock lines remain HIGH.

Start data transfer: A change in the state of the data line, from HIGH to LOW, while the clock is HIGH,

defines a START condition.

Stop data transfer: A change in the state of the data line, from LOW to HIGH, while the clock line is

HIGH, defines the STOP condition.

Data valid: The state of the data line represents valid data when, after a START condition, the data line is

stable for the duration of the HIGH period of the clock signal. The data on the line must be changed

during the LOW period of the clock signal. There is one clock pulse per bit of data.

Each data transfer is initiated with a START condition and terminated with a STOP condition. The

number of data bytes transferred between START and STOP conditions is not limited, and is determined

by the master device. The information is transferred byte-wise and each receiver acknowledges with a

ninth bit. Within the bus specifications a regular mode (100 kHz clock rate) and a fast mode (400 kHz

clock rate) are defined. The DS1682 only supports the standard mode of operations.