DS1602

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OPERATION

The main elements of the DS1602 are shown in Figure 1. As shown, communications to and from the

select, register clear, and oscillator trim information. Each bit is serially input on the rising edge of the

clock input. After the first eight clock cycles have loaded the protocol register with a valid protocol,

must be connected to the battery. This will keep the DS1602 out of battery backup mode. Battery

powered operation down to 2.5V is possible with reduced speed performance on the serial port.

PROTOCOL REGISTER

The protocol bit definition is shown in Figure 2. Valid protocols and the resulting actions are shown in

Table 1. Each data transfer to the protocol register designates what action is to occur. As defined, the

MSB (bit 7 which is designated ACC) selects the 32–bit continuous counter for access. If ACC is a

logical 1 the continuous counter is selected and the 32 clock cycles that follow the protocol will either

read or write this counter. If the counter is being read, the contents will be latched into a different register

at the end of protocol and the latched contents will be read out on the next 32 clock cycles. This avoids

reading garbled data if the counter is clocked by the oscillator during a read. Similarly, if the counter is to

be written, the data is buffered in a register and all 32 bits are jammed into the counter simultaneously on

the rising edge of the 32

CC

active counter for access. If AVC is a logical 1 this counter is selected and the 32 clock cycles that follow

will either read or write this counter. If both bit 7 and bit 6 are written to a logic high, all clock cycles

beyond the protocol are ignored and bits 5, 4, and 3 are loaded into the oscillator trim register. A value of

binary 3 (011) will give a clock accuracy of ±120 seconds per month at 25

°C. Increasing the binary

number towards 7 will cause the real time clock to run faster. Conversely, lowering the binary number

towards 0 will cause the clock to run slower. Binary 000 will stop the oscillator completely. This feature

maximum. In applications where oscillator trimming is not practical or not needed, a default setting of

011 is recommended. Bit 2 of protocol (designated CCC) is used to clear the continuous counter. When

logical 1. Bit 0 of the protocol (designated RD) determines whether the 32 clocks to follow will write a

counter or read a counter. When RD is set to a logical 0 a write action will follow when RD is set to a

logical 1 a read action will follow. When sending the protocol, 8 bits should always be sent. Sending less

than 8 bits can produce erroneous results. If clearing the counters or trimming the oscillator, the data

transfer can be terminated after the 8–bit protocol is sent. However, when reading or writing the counters,

32 clock cycles should always follow the protocol.

RESET AND CLOCK CONTROL

RST

turns on the serial port logic which allows access to the protocol register for the protocol data entry.

transfer. A clock cycle is a sequence of a falling edge followed by a rising edge. For write inputs, data

must be valid during the rising edge of the clock. Data bits are output on the falling edge of the clock