DS1075

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READ/WRITE TIME SLOTS

The definitions of write and read time slots are illustrated below. All time slots are initiated by the master

driving the data line low. The falling edge of the data line synchronizes the DS1075 to the master by

triggering a delay circuit in the DS1075. During write time slots, the delay circuit determines when the

DS1075 will sample the data line. For a read data time slot, if a “0” is to be transmitted, the delay circuit

determines how long the DS1075 will hold the data line low overriding the 1 generated by the master. If

the data bit is a “1”, the DS1075 will leave the read data time slot unchanged.

WRITE “1” TIME SLOT Figure 14

WRITE “0” TIME SLOT Figure 15