W152
2
Overview
The W152 products are eight-output zero delay buffers. A
Phase-Locked Loop (PLL) is used to take a time-varying signal
and provide eight copies of that same signal out. The external
feedback to the PLL provides outputs in phase with the refer-
ence inputs.
Internal dividers exist in some options allowing the user to get
a simple multiple (/2, x2, x4) of the reference input, for details
see Table 1. Because the outputs are separated into two
banks, it is possible to provide some combination of these mul-
tiples at the same time.
Spread Aware
Many systems being designed now utilize a technology called
Spread Spectrum Frequency Timing Generation. Cypress has
been one of the pioneers of SSFTG development, and we de-
signed this product so as not to filter off the Spread Spectrum
feature of the Reference input, assuming it exists. When a zero
delay buffer is not designed to pass the SS feature through,
the result is a significant amount of tracking skew which may
cause problems in systems requiring synchronization.
For more details on Spread Spectrum timing technology,
please see the Cypress application note titled, “EMI Suppres-
sion Techniques with Spread Spectrum Frequency Timing
Generator (SSFTG) ICs.”
Functional Description
Logic inputs provide the user the ability to turn off one or both
banks of clocks when not in use, as described in Table 2. Dis-
abling a bank of unused outputs will reduce jitter and power
consumption, and will also reduce the amount of EMI generat-
ed by the W152.
These same inputs allow the user to bypass the PLL entirely if
so desired. When this is done, the device no longer acts as a
zero delay buffer, it simply reverts to a standard eight-output
clock driver.
The W152 PLL enters an auto power-down mode when there
are no rising edges on the REF input. In this mode, all outputs
are three-stated and the PLL is turned off.
Pin Definitions
Pin Name
Pin No.
Pin
Type
Pin Description
REF
1
I
Reference Input: The output signals QA0:3 through QB0:3 will be synchronized to
this signal unless the device is programmed to bypass the PLL.
FBIN
16
I
Feedback Input: When programmed to zero delay buffer mode, this input must be
fed by one of the outputs (QA0:3 or QB0:3) to ensure proper functionality. If the trace
between FBIN and the output pin being used for feedback is equal in length to the
traces between the outputs and the signal destinations, then the signals received at
the destinations will be synchronized to the REF signal input.
QA0:3
2, 3, 14, 15
O
Outputs from Bank A: The frequency of the signals provided by these pins is deter-
mined by the feedback signal connected to FBIN, and the specific W152 option being
used. See Table 2.
QB0:3
6, 7, 10, 11
O
Outputs from Bank B: The frequency of the signals provided by these pins is deter-
mined by the feedback signal connected to FBIN, and the specific W152 option being
used. See Table 2.
VDD
4, 13
P
Power Connections: Connect to 3.3V. Use ferrite beads to help reduce noise for
optimal jitter performance.
GND
5, 12
G
Ground Connections: Connect all grounds to the common system ground plane.
SEL0:1
9, 8
I
Function Select Inputs: Tie to VDD (HIGH, 1) or GND (LOW, 0) as desired per
Table 2.
Table 2. Input Logic
SEL1
SEL0
QA0:3
QB0:3
PLL
0
0
Three-State Three-State
Shutdown
0
1
Active
Three-State
Active, Utilized
1
0
Active
Active
Shutdown,
Bypassed
1
1
Active
Active
Active, Utilized
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