CPC7583

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9

Rev. E

Table 13. Truth Table for the CPC7583BC and CPC7583BD

INring

INtestin

INtestout

TSD

TESTin

Break

RingTest

Ring

TESTout

Switches

Switches

Switches

Switches

Switches

0V

0V

0V

Off

On

Off

Off

0V

0V

5V

Off

Off

Off

Off

0V

5V

0V

On

Off

Off

Off

5V

0V

0V

Off

Off

Off

On

5V

5V

0V

Off

Off

On

Off

0V

5V

5V

On

Off

Off

Off

5V

0V

5V

Off

Off

Off

Off

5V

5V

5V

Off

Off

On

Off

Don’t

Don’t

Don’t

Off

Off

Off

Off

Care

Care

Care

1

If TSD = 5V, the thermal shutdown mechanism is disabled.

If TSD if floating, the thermal shutdown mechanism is active.

2

Forcing TSD to ground overrides the logic input pins and forces an all off state.

3

Idle/Talk State.

4

TESTout state.

5

TESTin state.

6

Power Ringing State.

7

Ringing generator test state.

8

Simultaneous TESTout and TESTin state.

9

All OFF State

A parallel in/parallel out data latch is integrated into the CPC7583. Operation of the data latch is controlled by the logic level input pin

LATCH. The data input to the latch is the INPUT pin of the CPC7583 and the output of the data latch is an internal node used for state

control.

When the LATCH control pin is at logic 0, the data latch is transparent and data control signals flow directly from INPUT, through the data

latch to state control. Any changes in INPUT will be reflected in the state of the switches.

When the LATCH control pin is at logic 1, the data latch is active; the CPC7583 will no longer react to changes at the INPUT control pin. The

state of the switches is now latched; that is, the state of the switches will remain as they were when the LATCH input transitioned from logic

0 to logic 1. The switches will not respond to changes in INPUT as long as LATCH is held high.

Note that the Tsd input is not tied to the data latch. Tsd is not affected by the LATCH input. Tsd input will override state control via INPUT

and LATCH.