CS5333

12

DS520PP1

Left/Right Clock

7

LRCK (

Input/Output) - The Left/Right clock determines which channel is currently being

output on the serial audio data line SDOUT. The frequency of the Left/Right clock must be

at the input sample rate. The required relationship between the Left/Right clock, serial

clock and serial data is defined by the DIF pin.

MCLK Divide

Enable

8

DIV (

Input) - This pin serves different functions in Master and Slave modes.

In Master mode: When high, the chip will enter High Rate Mode; When this pin is low, the

chip will enter Base Rate Mode.

In Slave mode: When high, MCLK is divided internally by 2; When low, MCLK is not

changed.

Digital Interface

Format

9

DIF (

Input) - The required relationship between the Left/Right clock, serial clock and serial

data is defined by the Digital Interface Format.

Test Input

10

TST (

Input) - Must be connected directly to ground.

Positive Voltage

Reference

11

FILT+ (

Output) - Positive reference for internal sampling circuits. An external capacitor is

required from FILT+ to ground, as shown in Figure 3. The recommended value will typi-

cally provide 60 dB of PSRR at 1 kHz and 40 dB of PSRR at 60 Hz. FILT+ is not intended

to supply external current. FILT+ has a typical source impedance of 250 k

Ω and any cur-

rent drawn from this pin will alter device performance.

Reference Ground

12

REF_GND (

Input) - Ground reference for the internal sampling circuits. Must be con-

nected to ground.

Analog Inputs

13,14

AINR, AINL (

Input) - The full scale analog input level is specified in the Analog Character-

istics specification table.

Quiescent Voltage

15

VQ (

Output) - Filter connection for internal A/D converter quiescent reference voltage. A

capacitor must be connected from VQ to ground. VQ is not intended to supply external

current. VQ has a typical source impedance of 250 k

Ω and any current drawn from this pin

will alter device performance.

Reset

16

RST (

Input) - When low the device enters a low power mode and the part is in reset.

When high, the part returns to normal operation within 1024 LRCK cycles.

DIF

DESCRIPTION

0

1

Left Justified, up to 24-bit data

Table 2. Digital Interface Format - DIF