CS5333

DS520PP1

11

3. PIN DESCRIPTION

Interface Power

VL

RST

Reset

Master Clock

MCLK

VQ

Quiescent Voltage

Serial Clock

SCLK

AINL

Left Channel Analog Input

Serial Data Output

SDATA

AINR

Right Channel Analog Input

Analog Power

VA

REF_GND Reference Ground

Ground

GND

FILT+

Positive Voltage Reference

Left Right Clock

LRCK

TST

Test Input

MCLK Divide

DIV

DIF

Digital Interface Format

1

2

3

4

5

6

7

8

5

1

2

6

16

15

14

13

12

11

10

9

1

2

3

4

5

6

7

8

5

1

2

6

16

15

14

13

12

11

10

9

Sample

Rate

(kHz)

MCLK (MHz)

HRM

BRM

128x

192x

256x*

384x*

256x

384x

512x

768x*

1024x*

32

4.0960

6.1440

8.1920

12.2880

8.1920

12.2880

16.3840

24.5760

32.7680

44.1

5.6448

8.4672

11.2896

16.9344

11.2896

16.9344

22.5792

32.7680

45.1584

48

6.1440

9.2160

12.2880

18.4320

12.2880

18.4320

24.5760

36.8640

49.1520

64

8.1920

12.2880

16.3840

24.5760

-

-

-

-

-

88.2

11.2896

16.9344

22.5792

33.8688

-

-

-

-

-

96

12.2880

18.4320

24.5760

36.8640

-

-

-

-

-

* DIV= Hi

Table 1. Common Clock Frequencies

Interface Power

1

VL (

Input) - Digital interface power supply. Typically 1.8 to 3.3 VDC.

Master Clock

2

MCLK (

Input) - The master clock frequency must be either 256x, 384x, 512x, 768x or

1024x the input sample rate in Base Rate Mode (BRM) and 128x, 192x, 256x, 384x the

input sample rate in High Rate Mode (HRM). Table 1 illustrates several standard audio

sample rates and the required master clock frequencies.

Serial Clock

3

SCLK (

Input/Output) - Clocks the individual bits of the serial data out of the SDOUT pin.

The required relationship between the Left/Right clock, serial clock and serial data is

defined by the DIF pin.

Serial Audio Data

Out (M/S select)

4

SDATA (

Output) - This pin serves two functions.

First: two’s complement MSB-first serial data is output on this pin. The data is clocked out

of SDOUT via the serial clock and the channel is determined by the Left/Right clock. The

required relationship between the Left/Right clock, serial clock and serial data is defined

by the DIF pin.

Second: Master/Slave mode selection is determined, at startup, by a 47 kOhm pullup/pull-

down on this line. A pullup to VL selects Master mode and a pulldown to GND selects

Slave mode.

Analog Power

5

VA (

Input) - Analog power supply. Typically 1.8 to 3.3 VDC.

Ground

6

GND (

Input) - Ground Reference.