CS5317 datasheet(28/32 Pages) CIRRUS

28 / 32 page

the board and then connected to the VA+ and VA-

supply pins of the chip. The +5 V and -5V are

then connected by means of ten

Ω resistors to the

VD+ and VD- pins respectively. Capacitive filter-

ing is provided on all supply pins of the chip. In

addition there is a 0.1

µF filter capacitor con-

nected from the REFBUF pin of the chip to the

VA- supply pin.

To properly operate, the CS5317 chip requires an

external (5 V CMOS compatible) clock. A BNC

connector labeled CLKIN is provided to connect

the off-board clock signal to the board.

The

CLKIN signal is also available on the 40 pin

header connector. The CLKIN signal is one input

to the phase detector of the on-chip phase locked

loop of the CS5317.

Header connector P2 (see Figure 2) is provided to

allow mode selection for the CS5317 chip. The

mode selection works together with the CLKIN

signal to set the sample rate and the output word

rate of the CS5317. See the CS5317 data sheet

for details on mode selection. Two of the avail-

able modes (CLKG1 and CLKG2) utilize the

on-chip phase locked loop to step up the CLKIN

frequency to obtain the necessary sample rate

clock for the A/D converter. Another mode (the

CLKOR mode) does not use the on-chip PLL but

instead drives the sample function directly. The

UNUSED GATES

GND R

74HC74

C10

0.1

µF

C11

10k

0.1

µF

0.1

µF

(fig. 2)

DOUT

CLKOUT

(fig. 2)

DRDY

DACK

(fig. 6)

DOUT2

(fig. 6)

CLKOUT

(fig. 6)

CLKOUT2

DATA

DATA 1

(fig. 6)

DATA

(fig. 2)

TP3

TP2

Figure 3. Buffers and Parallel Handshake Flip-Flop

CDB5317

DS27DB3

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