MODE - Mode Set, PIN 7.

Determines the internal clocking mode utilized by the CS5317. Connect to +5V to select

CLKG1 mode. Connect to DGND to select CLKG2 mode. Connect to -5V to select CLKOR

mode. This pin becomes equivalent to FSYNC in the CSZ5316 compatible mode.

VCOIN - VCO Input, PIN 18.

This pin is typically connected to PHDT. A capacitor and resistor in series connected between

VA+ and this pin sets the filter response of the on-chip phase locked loop.

PHDT - Phase Detect, PIN 17.

This pin is typically connected to VCOIN. A capacitor and resistor in series connected between

VA+ and this pin sets the filter response of the on-chip phase locked loop.

Inputs

AIN - Analog Input, PIN 11.

DOE - Data Output Enable, PIN 3.

Three-state control for serial output interface. When low, DATA, DOUT, and CLKOUT are

active. When high, they are in a high impedance state.

RST - Sample Clock Reset, PIN 16.

Sets phase of CLKOUT. Functions only in the clock override mode, CLKOR. Used to

synchronize the output samples of multiple CS5317’s. Must be kept high in CLKG1 or CLKG2

modes. Also, tying this pin low, with MODE not tied to - 5V, will place the CS5317 into

CSZ5316 compatible mode.

Outputs

DOUT - Data Output Flag, PIN 8.

The falling edge indicates the start of serial data output on the DATA pin. The rising edge

indicates the end of serial data output.

DATA - Data Output, PIN 6.

Serial data output pin. Converted data is clocked out on this pin by the rising edge of

CLKOUT. Data is sent MSB first in two’s complement format.

CLKOUT - Data Output Clock, PIN 5.

Serial data output clock. Data is clocked out on the rising edge of this pin. The falling edge

should be used to latch data. Since CLKOUT is a free running clock, DOUT can be used to

indicate valid data.

REFBUF - Positive Voltage Reference Noise Buffer, PIN 12.

Used to attenuate noise on the internal positive voltage reference. Must be connected to the

analog ground through a 0.1

CS5317

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DS27F4