CS49400 datasheet(52/100 Pages) CIRRUS

52 / 100 page

host read a message. When the code supports

FINTREQ notification, the FINTREQ pin is

asserted (driven low) when the DSP has an

outgoing message for the host.

FINTREQ is useful for informing the host of

unsolicited

messages

without

polling.

unsolicited message is defined as a message

generated by the DSP without an associated host

read request. Unsolicited messages are used to

notify the host of conditions such as a change in the

incoming audio data type (e.g. PCM --> AC-3).

Most unsolicited messages must be specifically

enabled by setting the appropriate bit in the

application’s manager, enabling autodetection, or

enabling other host notification capabilities.

6.2.5.1 Writing a Byte in Intel Mode for DSPAB

Information provided in this section is intended as

a functional description of how to write control

information to DSPAB. The system designer must

ensure that all of the timing constraints of the Intel

Parallel Host Mode Write Cycle are met.

The flow diagram shown in Figure 36 illustrates

the sequence of events that define a one-byte write

in Intel mode. The protocol presented in Figure 36

will now be described in detail.

1) The host must first drive the FA1 and FA0

address of the desired Parallel I/O Register. The

address must be maintained for the duration of

the write cycle.

Host Message: FA[1:0]==00b.

Host Control:

FA[1:0]==01b.

PCMDATA:

FA[1:0]==10b.

CMPDATA:

FA[1:0]==11b.

2) The host then indicates that the selected register

will be written. The host initiates a write cycle

by driving the FCS and FWR pins low.

3) The host drives the data byte to the FDAT[7:0]

pins of DSPAB.

4) Once the setup time for the write has been met,

the host ends the write cycle by driving the FCS

and FWR pins high.

6.2.5.2 Reading a Byte in Intel Mode for DSPAB

Information provided in this section is intended as

a functional description of how to read control

information from DSPAB. The system designer

must ensure that all of the timing constraints of the

Intel Parallel Host Mode Read Cycle are met.

The flow diagram shown in Figure 37 illustrates

the sequence of events that define a one-byte read

in Intel mode. The protocol presented in Figure 37

will now be described in detail.

1) The host must first drive the FA1 and FA0

address of the desired Parallel I/O Register.

Note that only the Host Message register and

the Host Control register can be read. The

address must be maintained for the duration of

the read cycle.

Host Message: FA[1:0]==00b.

Host Control:

FA[1:0]==01b.

2) The host initiates a read cycle by driving the

FCS and FRD pins low (bus must be tri-stated

FCS (HIGH)

FWR (HIGH)

WRITE BYTE TO

FDAT[7:0]

FCS (LOW)

FWR (LOW)

ADDRESS A PARALLEL I/O REGISTER

(FA[1:0] SET APPROPRIATELY)

Figure 36. Intel Mode, One-Byte Write Flow Diagram

for DSPAB

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