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CS49400 датащи(PDF) 68 Page - Cirrus Logic |
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CS49400 датащи(HTML) 68 Page - Cirrus Logic |
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68 / 100 page ![]() 68 Message Register. 3) Once the host knows that the DSP is ready for a new control word, it should write the 32-bit control word to the Host Message Register (FA[1:0] = 00b) using the selected communication mode (Intel or Motorola). 4) If the host would like to write any more 32-bit control words to DSPC, the host should once again poll the Host Control Register (return to step 1). 6.3.7.2 Control Read in a Parallel Host Mode for DSPC When reading control data from DSPC, the same protocol is used whether the host is reading a single 32-bit word, or a string of message words. Reads and writes to the Host Message Register are always 32-bits (4-bytes), and reads of the Host Control Register are always a single byte. The example shown in this section can be used for any control read situation. The generic function ‘Read_Word_*()’ is used in the following example as a generalized reference to either Read_Word_MOT() (Motorola 32-bit word read) or Read_Word_INT() (Intel 32-bit word read). Figure 51 shows a typical read sequence. The protocol presented in Figure 51 will now be described in detail. 1) Optionally, INTREQ going low may be used as an interrupt to the host to indicate that DSPC has an outgoing message. 2) The host reads the Host Control Register (A[1:0] = 01b) in order to determine the state of the communication interface. 3) In order to determine whether DSPC has an outgoing control word that is valid, the host must check the HOUTRDY bit of the Host Control Register (bit 1, A[1:0] = 01b). If HOUTRDY is high, then the Host Message Register contains a valid 32-bit word for the host. If HOUTRDY is low, then the DSP has not placed a new control word in the Host Message Register, and the host should poll the Host Control Register again. 4) Once the host knows that the DSP is ready to provide a new 32-bit response word, the host can safely read a word from the Host Message Register (A[1:0] = 00b) using the appropriate communication protocol (Motorola or Intel). 5) If the host expects to read more 32-bit response words, the host should once again check the FINTREQ = 0? MORE WORDS TO READ? FINISHED READ_BYTE_*( HOST CONTROL REGISTER) Y N READ_WORD_*( HOST MESSAGE REGISTER) HOUTRDY == 1 Y N Y READ_BYTE_*( HOST CONTROL REGISTER) HOUTRDY == 1 WAIT 100 MICROSEC Y N Figure 51. Typical Parallel Host Mode Control Read Sequence Flow Diagram for DSPC |
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