CS4610 datasheet(20/29 Pages) CIRRUS

20 / 29 page

DS241PP5

CS4610/11

CrystalClear™ SoundFusion™ PCI Audio Accelerator

ence of an external EEPROM device and load the

Subsystem ID and Subsystem Vendor ID fields,

along with two bytes of general configuration in-

formation, into internal registers. At power-up, the

CS4610/11 will attempt to read from the external

device, and will check the data received from the

device for a valid signature header. If the header

data is invalid, the data transfer is aborted. After

power-up, the host can read or write from/to the

EEPROM device by accessing specific registers in

the CS4610/11. Cirrus Logic provides software to

program the EEPROM.

The two wire interface for the optional external EE-

PROM device is depicted in Figure 15. During data

transfers, the data line (EEDAT) can change state

only while the clock signal (EECLK) is low. A

state change of the data line while the clock signal

is high indicates a start or stop condition to the EE-

PROM device.

The EEPROM device read access sequence is

shown in the Figure 16. The timing follows that of

a random read sequence. The CS4610/11 first per-

forms a “dummy” write operation, generating a

start condition followed by the slave device address

and the byte address of zero. The slave address is

made up of a device identifier (0xA) and a bank se-

lect (bits A2-A0). The CS4610/11 always begins

access at byte address zero and continues access a

byte at a time. The byte address automatically in-

crements by one until a stop condition is detected.

The CS4610/11 will read a total of seven bytes

from the EEPROM.

General Purpose I/O Pins

Many of the CS4610/11 signal pins are internally

multiplexed to serve different functions depending

on the environment in which the device is being

used. Several of the CS4610/11 signal pins may be

used as general purpose I/O pins when not required

for other specific functions in a given application.

CS4610/11

Serial

EEPROM

EECLK

4.7 k

Ω

EEDAT

SCL

SDA

Figure 15. External EEPROM Connection

S 1010000 0 A 000000 00 AS 1010000 1 A

Data

Start

Part

Address

Start

Acknowledge

Stop

Acknowledge

Data

EEPROM

Write

Read

Bank

Address

Part

Address

DSP

Figure 16. External EEPROM Read Access Sequence

CS4610 датащи(PDF) 20 Page - Cirrus Logic

CS4610 датащи(HTML) 20 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29

датащи скачать

ссылки URL