16

DS241PP5

CS4610/11

CrystalClear™ SoundFusion™ PCI Audio Accelerator

DACs to expand the audio output capability to six

channels. This expanded output capability is useful

for applications where discrete 5.1 channel output

is desired for Dolby AC-3 audio programs. The

connection diagram for the additional CS4333

DACs is given in Figure 11. The CS4333 DACs

share the SCLK output from the CS423x with the

CS4610. The CS4333 DACs also receive a 16.9344

MHz MCLK signal from the CS423x. Note that the

CS423x MCLK output has limited drive strength

and should be buffered in this application. The LR-

CLK framing clock and the SDO2/SDO3 digital

audio outputs are provided from the CS4610. The

SDO2 and SDO3 transitions occur on falling edges

of SCLK (the primary output SDOUT transitions

on rising edges of SCLK). LRCLK transitions oc-

cur on falling edges of SCLK, with the LRCLK

high phase indicating left channel data present on

SDO2/SDO3. SDO2/SDO3 data is right justified,

with 16 bits of zero pad followed by 16-bits of data,

transmitted MSB first. There are 64 SCLKs per

LRCLK, and MCLK runs at 384

× the frame rate.

The serial port clock and data timing relationship

for this configuration is indicated Figure 12. The

clock and data signal functions for this configura-

tion are summarized in Table 4.

AC’97 Controller Configuration

In this configuration the CS4610/11 functions as an

AC’97 controller. The CS4610/11 communicates

with an AC’97 Codec, such as the CrystalClear

Audio Codec ‘97 Specification version 1.03. A

block diagram for the AC’97 Controller Configura-

tion is given in Figure 7. The signal connections be-

tween the CS4610/11 and the AC’97 Codec are

indicated in Figure 13. In this configuration, the

AC’97 Codec is the timing master for the digital

audio link. The CS4610/11 ASDOUT output sup-

ports data transmission on all 10 possible sample

Pin Name Direction

Functional Description

SCLK

Input

Main timing driver for digital audio link, both edges used internally for timing. Also functions

as the source to the PLL for internal clock generation.

FSYNC

Input

Framing signal for digital audio link, high time indicates left channel data and low time indi-

cates right channel data. Frame is sampled on the falling edge of the SCLK input.

SDOUT

Output

Primary output port serial data pin. This data is the CS4610/11 output stream going to the

CS423x device. The serial data on this pin transitions on the rising edge of the SCLK input.

SDIN

Input

Primary input port serial data pin. This data contains both CS423x ADC data and the CS423x

output data. The serial data on this pin is sampled on the falling edge of the SCLK input.

Table 3. Serial Audio Port Signal Summary for CS4610/11 + CS423x Configuration

FSYNC

SCLK

SDOUT

SDIN

15

15 14 13

15 14

15 14 13

15 14

DAC 16 Clocks

15 14 13

15

15

ADC 16 Clocks

DAC 16 Clocks

ADC 16 Clocks

DAC 16 Clocks

Right Data

Left Data

...

DAC 16 Clocks

14 13

0

0

13

0

13

0

0

0

...

...

...

...

...

...

...

Figure 10. Serial Audio Port Format for CS4610/11 + CS423x Configuration