CS4329 datasheet(23/36 Pages) CIRRUS

23 / 36 page

CDB4329 CDB4390

DS153DB3

The transceiver operates as a transmitter with the

CLK SOURCE jumper in the 8412 position.

LRCK, SDATA, and SCLK from the CS8412 will

be available on J1. J22 must be in the 0 position and

J23 must be in the 1 position for MCLK to be an

output and to avoid bus contention on MCLK.

The transceiver operates as a receiver with the CLK

SOURCE jumper in the EXTERNAL position.

LRCK, SDATA and SCLK on J1 become inputs.

The CS8412 must be removed from the evaluation

board for operation in this mode.

There are 2 options for the source of MCLK in the

EXT CLK source mode. MCLK can be an input

with J23 in the 1 position and J22 in the 0 position.

However, the recommended mode of operation is

to generate MCLK on the evaluation board. MCLK

becomes an output with LRCK, SCLK and SDA-

TA inputs. This technique insures that the

CS4329/90 receives a jitter free clock to maximize

performance. This can be accomplished by install-

ing a crystal oscillator into U4, see Figure 9 (the

socket for U4 is located within the footprint for the

CS8412) and placing J22 in the 1 position and J23

in the 0 position.

Analog Filter

The design of the second-order Butterworth low-

pass filter, Figure 6, is discussed in the CS4329 and

CS4390 data sheets and the applications note "De-

sign Notes for a 2-pole Filter with Differential In-

put."

Grounding and Power Supply Decoupling

The CS4329/90 requires careful attention to power

supply and grounding arrangements to optimize

performance. The recommended power arrange-

ments would be VA+ connected to a clean +5 Volt

supply. The voltage VD+ (pin 6 of the CS4329/90)

should be derived from VA+ through a 2 ohm resis-

tor and should not used for any additional digital

circuitry. Ideally, mode pins which require this

voltage should be connected directly to VD+ (pin 6

of the CS4329/90) and mode pins which require

DGND should be connected directly to pin 5 of the

CS4329/90. AGND and DGND, Pins 4 and 5, are

connected together at the CS4329/90. However, it

was not possible to connect VD+ (pin 6 of the

CS4329/90) and DGND to the mode pins on the

CDB4329/90 due to layout complications resulting

from the hardware selected to exercise the features

of the CS4329/90.

Figure 2 shows the CS4329/90 and connections.

The evaluation board has separate analog and digi-

tal regions with individual ground planes. DGND

for the CS4329/90 should not be confused with the

ground for the digital section of the system (GND).

The CS4329/90 is positioned over the analog

ground plane near the digital/analog ground plane

split. These ground planes are connected elsewhere

on the board. This layout technique is used to min-

imize digital noise and to insure proper power sup-

ply

matching/sequencing.

The

decoupling

capacitors are located as close to the CS4329/90 as

possible. Extensive use of ground plane fill on both

the analog and digital sections of the evaluation

board yield large reductions in radiated noise ef-

fects.

CS4329 датащи(PDF) 23 Page - Cirrus Logic

CS4329 датащи(HTML) 23 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36

датащи скачать

ссылки URL