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CS4299 датащи(PDF) 33 Page - Cirrus Logic |
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CS4299 датащи(HTML) 33 Page - Cirrus Logic |
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33 / 52 page ![]() CS4299 33 5. POWER MANAGEMENT 5.1 AC ’97 Reset Modes The CS4299 supports three reset methods, as de- fined in the AC ’97 Specification: Cold AC ’97 Re- set, Warm AC ’97 Reset, Register AC ’97 Reset. A Cold Reset results in all AC ’97 logic (registers in- cluded) initialized to its default state. A Warm Re- set leaves the contents of the AC ’97 register set unaltered. A Register Reset initializes only the AC ’97 registers to their default states. 5.1.1 Cold AC ‘97 Reset A Cold Reset is achieved by asserting RESET# for a minimum of 1 µs after the power supply rails have stabilized. This is done in accordance with the minimum timing specifications in the AC ’97 Seri- al Port Timing section on page 7. Once deasserted, all of the CS4299 registers will be reset to their de- fault power-on states and the BIT_CLK and SDATA_IN signals will be reactivated. 5.1.2 Warm AC ’97 Reset A Warm Reset allows the AC-link to be reactivated without losing information in the CS4299 registers. A Warm Reset is required to resume from a D3hot state, where the AC-link had been halted yet full power had been maintained. A primary codec Warm Reset is initiated when the SYNC signal is driven high for at least 1 µs and then driven low in the absence of the BIT_CLK clock signal. The BIT_CLK clock will not restart until at least 2 nor- mal BIT_CLK clock periods (162.8 ns) after the SYNC signal is deasserted. A Warm Reset of the secondary codec is recognized when the primary codec on the AC-link resumes BIT_CLK genera- tion. The CS4299 will wait for BIT_CLK to be sta- ble to restore SDATA_IN activity and/or S/PDIF transmission on the following frame. 5.1.3 Register AC ’97 Reset The third reset mode provides a Register Reset to the CS4299. This is available only when the CS4299 AC-link is active and the Codec Ready bit is ‘set’. The audio (including extended audio) reg- isters (Index 00h - 38h) and the vendor specific reg- isters (Index 5Ah - 7Ah) are reset to their default states by a write of any value to the Reset Register (Index 00h). |
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