CS4294 datasheet(15/42 Pages) CIRRUS

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CS4294

DS326PP4

5.4.2

Read-Back Address Port (Slot 1)

RI[6:0]

has been requested in the previous frame. The Codec will only echo the register index for a read access.

Write accesses will not return valid data in Slot 1.

5.4.3

Read-Back Data Port (Slot 2)

RD[15:0]

16-bit register value. The Read-Back Data Port contains the register data requested by the Controller

from the previous read request. All read requests will return the read address in the Read-Back Address

Port (Slot 1) and the register data in the Read-Back Data Port (Slot 2) on the following serial data frame.

5.4.4

PCM Capture Data (Slot 3-11)

CD[17:0]

18-bit PCM (2’s compliment) data. The mapping of a given slot to an ADC is determined by the state of

the MD[1:0] bits found in the AC Mode Control (Index 5Eh) register.

5.4.5

GPIO Pin Status (Slot 12)

GI[9:0]

Status of the GPIO[8:3] pin.

IRQ

Set when the GPIO generates a wake up or interrupt cycle. See GPIO Pin Wake Up Mask (Index 52h)

The capture data in Slot [3:12] will only be valid when the respective slot valid bit is set in Slot 0.

5.5

AC ’97 Reset Modes

Three methods of resetting the CS4294, as defined

in the AC ’97 Specification, are supported: Cold

AC ’97 Reset, Warm AC ’97 Reset, and AC ’97

restart the AC-link when bit PR5 is set in the Power

Down Control/Status (Index 26h) register.

5.5.1 Cold AC ‘97 Reset

A Cold Reset is performed by asserting RESET# in

accordance with the minimum timing specifica-

tions in the Serial Port Timing section. Once de-as-

serted, all of the Codec’s registers will be reset to

their default power-on states and the BIT_CLK

clock and SDATA_IN signals will be reactivated.

The timing of power-up/reset events is discussed in

detail in the Power Management section.

5.5.2 Warm AC ’97 Reset

The CS4294 may also be reactivated when the AC-

link is powered down (refer to the PR4 bit descrip-

tion in the Power Management section) by a Warm

Reset. A Warm Reset allows the AC-link to be re-

activated without losing information in the Codec’s

registers. Warm Reset is initiated when the SYNC

signal is driven high for at least 1 µs and then driv-

en low in the absence of the BIT_CLK clock signal.

The BIT_CLK clock will not restart until at least 2

normal BIT_CLK clock periods

(± 162.8 ns) af-

ter the SYNC signal is de-asserted.

Bit 19

3210

RI6

RI5

RI4

RI3

RI2

RI1

RI0

Bit 19

RD15 RD14 RD13 RD12 RD11 RD10 RD9 RD8 RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0

Bit 19

987

6543

210

CD17 CD16 CD15 CD14 CD13 CD12 CD11 CD10 CD9 CD8 CD7 CD6 CD5 CD4 CD3 CD2 CD1 CD0

Bit 19

987

6543

210

GI8

GI7

GI6

GI5

GI4

GI3

IRQ

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