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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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CS51311GD14 датащи(PDF) 2 Page - Cherry Semiconductor Corporation |
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CS51311GD14 датащи(HTML) 2 Page - Cherry Semiconductor Corporation |
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2 / 19 page  2 Package Pin Description PACKAGE PIN # PIN SYMBOL FUNCTION Absolute Maximum Ratings Pin Symbol Pin Name VMAX VMIN ISOURCE ISINK Operating Junction Temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C Lead Temperature Soldering Reflow (SMD styles only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 sec. max above 183°C, 230°C peak Storage Temperature Range, TS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65° to 150°C ESD Susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2kV VCC IC Power Input 16V -0.3V N/A 1.5 APeak 200mA DC COMP Compensation Pin 6V -0.3V 1mA 5mA VFB, VOUT, VID0-4 Voltage Feedback Input, Output 6V -0.3V 1mA 1mA Voltage Sense Pin, Voltage ID DAC Inputs COFF Off-Time Pin 6V -0.3V 1mA 50mA GATE(H), GATE(L) High-Side, Low-Side FET Drivers 16V -0.3V DC 1.5APeak 1.5A Peak 200mA DC 200mA DC PWRGD Power-Good Output 6V -0.3V 1mA 30mA Gnd Ground 0V 0V 1.5A Peak N/A 200mA DC 1,2,3,4,5 VIDO – VID4 Voltage ID DAC inputs. These pins are internally pulled up to 5.65V if left open. VID4 selects the DAC range. When VID4 is high (logic one), the Error Amp reference range is 2.125V to 3.525V with 100mV increments. When VID4 is low (logic zero), the Error amp reference voltage is 1.325V to 2.075V with 50mV increments. 6VFB Error amp inverting input, PWM comparator non-inverting input, current limit comparator non-inverting input, PWRGD comparator input. 7VOUT Current limit comparator inverting input. 8VCC Input power supply pin for the internal circuitry. Decouple with filter capacitor to Gnd. 9 GATE(H) High side switch FET driver pin . 10 Gnd Ground pin. 11 GATE(L) Low side synchronous FET driver pin. 12 PWRGD Power-Good Output. Open collector output drives low when VFB is out of regulation. 13 COFF Off-Time Capacitor Pin. A capacitor from this pin to Gnd sets the off time for the regulator 14 COMP Error amp output. PWM comparator inverting input. A capacitor on this pin provides error amp compensation. |
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