CS51311GD14 datasheet(13/19 Pages) CHERRY

13 / 19 page

Once the total ESR of the input capacitors is known, the

input capacitor ripple voltage can be determined using the

formula:

VCIN(RMS) = ICIN(RMS) × ESRCIN,

where

VCIN(RMS) = input capacitor RMS voltage;

ICIN(RMS) = total input RMS current;

ESRCIN = total input capacitor ESR.

The designer must determine the input capacitor power

loss in order to ensure there isn’t excessive power dissipa-

tion through these components. The following formula is

used:

PCIN(RMS) = ICIN(RMS)2 × ESRCIN

where

PCIN(RMS) = input capacitor RMS power dissipation;

ICIN(RMS) = total input RMS current;

ESRCIN = total input capacitor ESR.

Step 6: Selection of the Input Inductor

A CPU switching regulator, such as the one in a buck

topology, must not disturb the primary +5V supply. One

method of achieving this is by using an input inductor and

a bypass capacitor. The input inductor isolates the +5V

supply from the noise generated in the switching portion

of the microprocessor buck regulator and also limits the

inrush current into the input capacitors upon power up.

The inductor’s limiting effect on the input current slew rate

becomes increasingly beneficial during load transients. The

worst case is when the CPU load changes from no load to

full load (load step), a condition under which the highest

voltage change across the input capacitors is also seen by

the input inductor. The inductor successfully blocks the

ripple current while placing the transient current require-

ments on the input bypass capacitor bank, which has to

initially support the sudden load change.

The minimum inductance value for the input inductor is

therefore:

LIN =

where

LIN = input inductor value;

∆V = voltage seen by the input inductor during a full

load swing;

(dI/dt)MAX = maximum allowable input current slew

rate (0.1A/µs for a Pentium® II power supply).

The designer must select the LC filter pole frequency so

that at least 40dB attenuation is obtained at the regulator

switching frequency. The LC filter is a double-pole net-

work with a slope of −2, a roll-off rate of –40dB/dec, and a

corner frequency:

fC =

where

L = input inductor;

C = input capacitor(s).

Step 7: Selection of the Switching FET

FET Basics

The use of the MOSFET as a power switch is propelled by

two reasons: 1) Its very high input impedance; and 2) Its very

fast switching times. The electrical characteristics of a MOS-

FET are considered to be those of a perfect switch. Control

and drive circuitry power is therefore reduced. Because the

input impedance is so high, it is voltage driven. The input

of the MOSFET acts as if it were a small capacitor, which

the driving circuit must charge at turn on. The lower the

drive impedance, the higher the rate of rise of VGS, and the

faster the turn- on time. Power dissipation in the switching

MOSFET consists of 1) conduction losses, 2) leakage losses,

3) turn-on switching losses, 4) turn-off switching losses,

and 5) gate-transitions losses. The latter three losses are

proportional to frequency. For the conducting power dissi-

pation rms values of current and resistance are used for

true power calculations. The fast switching speed of the

MOSFET makes it indispensable for high-frequency power

supply applications. Not only are switching power losses

minimized, but also the maximum usable switching fre-

quency is considerably higher. Switching time is indepen-

dent of temperature. Also, at higher frequencies, the use of

smaller and lighter components (transformer, filter choke,

filter capacitor) reduces overall component cost while

using less space for more efficient packaging at lower

weight.

The MOSFET has purely capacitive input impedance. No

DC current is required. It is important to keep in mind the

drain current of the FET has a negative temperature coeffi-

cient. Increase in temperature causes higher on-resistance

and greater leakage current. For switching circuits, VDS(ON)

should be low to minimize power dissipation at a given ID,

and VGS should be high to accomplish this. MOSFET

switching times are determined by device capacitance,

stray capacitance, and the impedance of the gate drive cir-

cuit. Thus the gate driving circuit must have high momen-

tary peak current sourcing and sinking capability for

switching the MOSFET. The input capacitance, output

capacitance and reverse-transfer capacitance also increase

with increased device current rating.

Two considerations complicate the task of estimating

switching times. First, since the magnitude of the input

capacitance, CISS, varies with VDS, the RC time constant

determined by the gate-drive impedance and CISS changes

during the switching cycle. Consequently, computation of

the rise time of the gate voltage by using a specific gate-

drive impedance and input capacitance yields only a rough

estimate. The second consideration is the effect of the

“Miller” capacitance, CRSS, which is referred to as CDG in

the following discussion. For example, when a device is on,

VDS(ON) is fairly small and VGS is about 12V. CDG is

charged to VDS(ON) − VGS, which is a negative potential if

the drain is considered the positive electrode. When the

drain is “off”, CDG is charged to quite a different potential.

In this case the voltage across CDG is a positive value since

the potential from gate-to-source is near zero volts and VDS

is essentially the drain supply voltage. During turn-on and

turn-off, these large swings in gate-to-drain voltage tax the

current sourcing and sinking capabilities of the gate drive.

In addition to charging and discharging CGS, the gate drive

must also supply the displacement current required by

2π LC

∆V

(dI/dt)MAX

Application Information: continued

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