5

Package Pin Description: continued

PACKAGE PIN #

PIN SYMBOL

FUNCTION

+

-

4.75V

DISABLE

1.33

55µA

VREF = 5V

OSC

Discharge

Latch

2.5V

PWM

Comp

S

R

Q

+

E/A

+

–

START

STOP

+

-

Clamp

SS

Clamp

12.5µA

OV

Monitor

UV

Monitor

∑

+

–

0.1V

0.1

+

–

53µA

2V

Vcc_OK

SS

Monitor

Monitor

+

–

1.45V

55ns

Blank

×

0.8

10k

20k

13.5V

2.5V

4.3V

200ns

G1

F1

G2

D1

Q2

G3

FAULT

ZD1

D4

+

–

4.7V

D2

D3

SS

PGnd

GATE

SLOPE

COMP

OV

LGnd

SYNC

UV

×

G4

×

SLEEP

2nd

Threshold

Figure 1: CS51021/22/23/24 Block Diagram

Block Diagram

16L PDIP & SO Narrow

Voltage at this pin sets pulse-by-pulse overcurrent threshold, and

second threshold (1.33 times higher) with Soft Start retrigger (hic-

cup mode).

Feedback voltage input. Connected to the error amplifier invert-

ing input.

10

COMP

Error amplifier output. Frequency compensation network is usu-

11

SS

Charging external capacitor restricts error amplifier output volt-

age during the start or fault conditions (hiccup).

12

LGnd

Logic ground.

13

5.0V reference voltage output.

14

Logic supply voltage.

15

PGnd

Output power stage ground connection.

16

Output power stage supply voltage.