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CS51021 датащи(PDF) 8 Page - Cherry Semiconductor Corporation |
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CS51021 датащи(HTML) 8 Page - Cherry Semiconductor Corporation |
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8 / 9 page ![]() 8 timing capacitor’s discharge current is trimmed, the maxi- mum duty cycle is well defined. It is determined by the ratio between the timing resistor RT and the timing capaci- tor CT. Refer to figures 5 and 6 to select appropriate values for RT and CT. fSW = ; TSW = tCH + tDIS Figure 5: Frequency vs. RT for Discrete Capacitor Values. Figure 6: Duty Cycle vs. RT for Discrete Capacitor Values. 90 80 70 60 50 40 10 15 20 25 30 35 540 45 50 RT (kΩ) 2 3 4 5 6 7 8 55 100 1 1. CT = 47pF 2. CT = 100pF 3. CT = 150pF 4. CT = 220pF 5. CT = 390pF 6. CT = 470pF 7. CT = 560pF 8. CT = 680pF 2500 2000 1500 1000 500 0 10 15 20 25 30 35 540 45 50 RT (kΩ) 1 2 3 4 5 6 7 8 1. CT = 47pF 2. CT = 100pF 3. CT = 150pF 4. CT = 220pF 5. CT = 390pF 6. CT = 470pF 7. CT = 560pF 8. CT = 680pF 1 TSW Circuit Description: continued |
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