Conversion Guide: P33 130nm to 65nm

Application Note

Sep 2008

8

Order Number: 320005-04

Notes:

1.

A1 is the least significant address bit.

2.

A24 is valid for 256-Mbit densities and above; otherwise, it is a no connect (NC).

3.

A25 is valid for 512-Mbit densities; otherwise, it is a no connect (NC).

3.2

TSOP Pinout

The TSOP Pinout is available and compatible for both P33 130nm and P33 65nm

products. Pin 13 on P33 130nm is connected to Vcc. For P33 65nm this pin has no

internal connection; it may be driven or left floated

1.

A1 is the least significant address bit.

2.

A24 is valid for 256-Mbit densities; otherwise, it is a no connect (NC).

3.

No Internal Connection on VCC Pin 13; it may be driven or floated. For legacy designs, pin can be tied to Vcc

Figure 2: 56-Lead TSOP Pinout (256-Mbit)

Numonyx

™

P33 Flash Memory

56-Lead TSOP Pinout

14 mm x 20 mm

Top View

1

3

4

2

5

7

8

6

9

11

12

10

13

15

16

14

17

19

20

18

21

23

24

22

25

27

28

26

56

54

53

55

52

50

49

51

48

46

45

47

44

42

41

43

40

38

37

39

36

34

33

35

32

30

29

31

A14

A13

A12

A10

A9

A11

A23

A21

VSS

A22

VCC

WP#

A20

WE#

A19

A8

A7

A18

A6

A4

A3

A5

A2

RFU

VSS

A24

WAIT

DQ15

DQ7

A17

DQ14

DQ13

DQ5

DQ6

DQ12

ADV#

CLK

DQ4

RST#

A16

DQ3

VPP

DQ10

VCCQ

DQ9

DQ2

DQ1

DQ0

VCC

DQ8

OE#

CE#

A1

VSS

A15

DQ11