OPA656 datasheet(12/25 Pages) NSC

12 / 25 page

OPA656

SBOS196G

www.ti.com

OPERATING SUGGESTIONS

SETTING RESISTOR VALUES TO MINIMIZE NOISE

The OPA656 provides a very low input noise voltage while

requiring a low 14mA quiescent supply current. To take full

advantage of this low input noise, careful attention to the other

possible noise contributors is required. Figure 4 shows the op

amp noise analysis model with all the noise terms included. In

this model, all the noise terms are taken to be noise voltage or

current density terms in either nV/ Hz or pA/ Hz .

FIGURE 4. Op Amp Noise Analysis Model.

4kT

OPA656

4kT = 1.6E –20J

at 290

°K

√4kTR

The total output spot noise voltage can be computed as the

square root of the squared contributing terms to the output

noise voltage. This computation is adding all the contributing

noise powers at the output by superposition, then taking the

square root to get back to a spot noise voltage. Equation 1

shows the general form for this output noise voltage using

the terms shown in Figure 4.

(1)

kTR

I R

kTR NG

BN SS

BI F

(

) +









(

) +

Dividing this expression by the noise gain (GN = 1+RF/RG)

will give the equivalent input referred spot noise voltage at

the noninverting input as shown in Equation 2.

(2)

kTR

NNI

BN SS

BI F

(

) ++ 







Putting high resistor values into Equation 2 can quickly

dominate the total equivalent input referred noise. A source

impedance on the noninverting input of 3k

Ω will add a

Johnson voltage noise term equal to just that for the amplifier

itself (7nV/ Hz). While the JFET input of the OPA656 is ideal

for high source impedance applications, both the overall

bandwidth and noise will be limited by higher source imped-

ances in the noninverting configuration of Figure 1.

FREQUENCY RESPONSE CONTROL

Voltage-feedback op amps like the OPA656 exhibit decreas-

ing signal bandwidth as the signal gain is increased. In

theory, this relationship is described by the GBP shown in the

Electrical Characteristics. Ideally, dividing GBP by the

noninverting signal gain (also called the Noise Gain, or NG)

will predict the closed-loop bandwidth. In practice, this only

holds true when the phase margin approaches 90

°, as it does

in high-gain configurations. At low gains (increased feedback

factors), most high-speed amplifiers will exhibit a more com-

plex response with lower phase margin. The OPA656 is

compensated to give a maximally flat 2nd-order Butterworth

closed loop response at a noninverting gain of +2 (Figure 1).

This results in a typical gain of +2 bandwidth of 200MHz, far

exceeding that predicted by dividing the 230MHz GBP by 2.

Increasing the gain will cause the phase margin to approach

° and the bandwidth to more closely approach the pre-

dicted value of (GBP/NG). At a gain of +10 the OPA656 will

show the 23MHz bandwidth predicted using the simple

formula and the typical GBP of 230MHz.

Unity-gain stable op amps like the OPA656 can also be

bandlimited using a capacitor across the feedback resistor.

For the noninverting configuration of Figure 1, a capacitor

across the feedback resistor will decrease the gain with

frequency down to a gain of +1. For instance, to bandlimit the

gain of +2 design to 20MHz, a 32pF capacitor can be placed

in parallel with the 250

Ω feedback resistor. This will, how-

ever, only decrease the gain from 2 to 1. Using a feedback

capacitor to limit the signal bandwidth is more effective in the

inverting configuration of Figure 2. Adding that same capaci-

tor to the feedback of Figure 2 will set a pole in the signal

frequency response at 20MHz, but in this case it will continue

to attenuate the signal gain to below 1. However, the output

noise contribution due the input voltage noise of the OPA656

will still only be reduced to a gain of 1 with the addition of the

feedback capacitor.

DRIVING CAPACITIVE LOADS

One of the most demanding and yet very common load

conditions for an op amp is capacitive loading. Often, the

capacitive load is the input of an ADC—including additional

external capacitance which may be recommended to im-

prove ADC linearity. A high-speed, high open-loop gain

amplifier like the OPA656 can be very susceptible to de-

creased stability and closed-loop response peaking when a

capacitive load is placed directly on the output pin. When the

amplifier’s open loop output resistance is considered, this

capacitive load introduces an additional pole in the signal

path that can decrease the phase margin. Several external

solutions to this problem have been suggested. When the

primary considerations are frequency response flatness, pulse

response fidelity and/or distortion, the simplest and most

effective solution is to isolate the capacitive load from the

feedback loop by inserting a series isolation resistor between

OPA656 датащи(PDF) 12 Page - National Semiconductor (TI)

OPA656 датащи(HTML) 12 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

датащи скачать

ссылки URL