RX64M datasheet(2/67 Pages) RENESAS

2 / 67 page

RX64M Group

1. Overview

Under development Preliminary document

Specifications in this document are tentative and subject to change.

R01DS0173EJ0090 Rev.0.90

Page 2 of 67

Feb 28, 2014

Overview

1.1

Outline of Specifications

Table 1.1 lists the specifications in outline, and Table 1.2 gives a comparison of the functions of products in different

packages.

Table 1.1 shows the outline of maximum specifications, and the number of peripheral module channels differs

depending on the pin number on the package and the code flash memory capacity. For details, see Table 1.2,

Comparison of Functions for Different Packages.

Table 1.1

Outline of Specifications (1/9)

Classification

Module/Function

Description

CPU

 Maximum operating frequency: 120 MHz

 32-bit RX CPU (RX v2)

 Minimum instruction execution time: One instruction per state (cycle of the system

clock)

 Address space: 4-Gbyte linear

 Register set of the CPU

General purpose: Sixteen 32-bit registers

Control: Ten 32-bit registers

Accumulator: Two 72-bit registers

 Basic instructions: 75

 Floating-point instructions: 11

 DSP instructions: 23

 Addressing modes: 10

 Data arrangement

Instructions: Little endian

Data: Selectable as little endian or big endian

 On-chip 32-bit multiplier: 32 × 32 → 64 bits

 On-chip divider: 32 / 32 → 32 bits

 Barrel shifter: 32 bits

FPU

 Single precision (32-bit) floating point

 Data types and floating-point exceptions in conformance with the IEEE754 standard

Memory

Flash memory

(code flash)

 Capacity: 2 Mbytes, 2.5 Mbytes, 3 Mbytes, 4 Mbytes

 120 MHz, no-wait access

 On-board programming: Four types

 Off-board programming (parallel programmer mode)

E2 data flash

 Capacity: 64 Kbytes

 Programming/erasing: 100,000 times

RAM

 Capacity: 512 Kbytes

 120 MHz, no-wait access

RAM with ECC

 Capacity: 32 Kbytes

 120 MHz, single wait access

 SEC-DED (single error correction/double error detection)

Standby RAM

 Capacity: 8 Kbytes

 Operation synchronized with PCLKB: Up to 60 MHz, two-cycle access

Operating modes

 Operating modes by the mode-setting pins

Single-chip mode

Boot mode (for the SCI interface)

Boot mode (for the USB interface)

User boot mode

 Operating modes by register setting

Single-chip mode, user boot mode

On-chip ROM disabled extended mode

On-chip ROM enabled extended mode

 Endian selectable

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