ADSP-TS101S datasheet(13/48 Pages) AD

13 / 48 page

ADSP-TS101S

Rev. C

Page 13 of 48

May 2009

Table 5. Pin Definitions—External Port Bus Controls

Signal

Type

Term

Description

ADDR31–0

I/O/T

Address Bus. The DSP issues addresses for accessing memory and peripherals on these pins. In

a multiprocessor system, the bus master drives addresses for accessing internal memory or I/O

processor registers of other ADSP-TS101S processors. The DSP inputs addresses when a host or

another DSP accesses its internal memory or I/O processor registers.

DATA63–0

I/O/T

External Data Bus. Data and instructions are received, and driven by the DSP, on these pins.

I/O/T (pu

Memory Read. RD is asserted whenever the DSP reads from any slave in the system, excluding

SDRAM. When the DSP is a slave, RD is an input and indicates read transactions that access its

internal memory or universal registers. In a multiprocessor system, the bus master drives RD.

The RD pin changes concurrently with ADDR pins.

WRL2

I/O/T (pu3)nc

Write Low. WRL is asserted in two cases: When the ADSP-TS101S writes to an even address word

of external memory or to another external bus agent; and when the ADSP-TS101S writes to a

32-bit zone (host, memory, or DSP programmed to 32-bit bus). An external master (host or DSP)

asserts WRL for writing to a DSP’s low word of internal memory. In a multiprocessor system, the

bus master drives WRL. The WRL pin changes concurrently with ADDR pins. When the DSP is a

slave, WRL is an input and indicates write transactions that access its internal memory or

universal registers.

WRH2

I/O/T (pu3)nc

Write High. WRH is asserted when the ADSP-TS101S writes a long word (64 bits) or writes to an

odd address word of external memory or to another external bus agent on a 64-bit data bus.

An external master (host or another DSP) must assert WRH for writing to a DSP’s high word of

64-bit data bus. In a multiprocessing system, the bus master drives WRH. The WRH pin changes

concurrently with ADDR pins. When the DSP is a slave, WRH is an input and indicates write

transactions that access its internal memory or universal registers.

ACK

I/O/T

epu

Acknowledge. External slave devices can deassert ACK to add wait states to external memory

accesses. ACK is used by I/O devices, memory controllers, and other peripherals on the data

phase. The DSP can deassert ACK to add wait states to read accesses of its internal memory. The

ADSP-TS101S does not drive ACK during slave writes. Therefore, an external (approximately

10 k

) pull-up is required.

BMS2, 4

O/T

(pu/pd3)

Boot Memory Select. BMS is the chip select for boot EPROM or flash memory. During reset, the

DSP uses BMS as a strap pin (EBOOT) for EPROM boot mode. When the DSP is configured to

boot from EPROM, BMS is active during the boot sequence. Pull-down enabled during RESET

(asserted); pull-up enabled after RESET (deasserted). In a multiprocessor system, the DSP bus

master drives BMS. For details see Reset and Booting on Page 9 and the EBOOT signal

description in Table 16 on Page 19.

MS1–0

O/T (pu

3)nc

Memory Select. MS0 or MS1 is asserted whenever the DSP accesses memory banks 0 or 1,

respectively. MS1–0 are decoded memory address pins that change concurrently with ADDR

pins. When ADDR31:26 = 0b000010, MS0 is asserted. When ADDR31:26 = 0b000011, MS1 is

asserted. In multiprocessor systems, the master DSP drives MS1–0.

Type column symbols: A = asynchronous; G = ground; I = input; O = output; o/d = open drain output; P = power supply;

pd = internal pull-down approximately 100 k; pu = internal pull-up approximately 100 k; T = three-state

Term (for termination) column symbols: epd = external pull-down approximately 10 k to VSS; epu = external pull-up approximately 10 k

to VDD-IO, nc = not connected; au = always used.

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