5-70

FAST AND LS TTL DATA

SN54/74LS73A

tPHL

tPHL

tPLH

Figure 1. Clock to Output Delays, Data

Set-Up and Hold Times, Clock Pulse Width

Figure 2. Set and Clear to Output Delays,

Set and Clear Pulse Widths

AC WAVEFORMS

tW

1.3 V

1.3 V

tW

1.3 V

1.3 V

1.3 V

1.3 V

1.3 V

1.3 V

tPLH

tPHL

tPLH

tPHL

SET

CLEAR

Q

Q

*The shaded areas indicate when the input is permitted to change for predictable output performance.

J or K *

CP

Q

Q

1.3 V

1.3 V

1.3 V

1.3 V

1.3 V

1.3 V

1.3 V

1.3 V

ts(L)

th(L) = 0

tW(L)

ts(H)

th(H) = 0

tW(H)

tPLH

1

fMAX