5-68

FAST AND LS TTL DATA

DUAL JK NEGATIVE

EDGE-TRIGGERED FLIP-FLOP

The SN54LS / 74LS73A offers individual J, K, clear, and clock inputs. These

dual flip-flops are designed so that when the clock goes HIGH, the inputs are

enabled and data will be accepted. The logic level of the J and K inputs may

be allowed to change when the clock pulse is HIGH and the bistable will per-

form according to the truth table as long as minimum set-up times are ob-

served. Input data is transferred to the outputs on the negative-going edge of

the clock pulse.

LOGIC DIAGRAM (Each Flip-Flop)

Q

K

13 (8)

3 (10)

Q

12 (9)

CLEAR

2 (6)

J

14 (7)

1 (15)

CLOCK (CP)

MODE SELECT — TRUTH TABLE

OPERATING MODE

INPUTS

OUTPUTS

OPERATING MODE

CD

J

K

Q

Q

Reset (Clear)

Toggle

Load “0” (Reset)

Load “1” (Set)

Hold

L

H

H

H

H

X

h

l

h

l

X

h

h

l

l

L

q

L

H

q

H

q

H

L

q

H, h = HIGH Voltage Level

L, I = LOW Voltage Level

X = Don’t Care

l, h (q) = Lower case letters indicate the state of the referenced input (or output) one set-up time

SN54/74LS73A

DUAL JK NEGATIVE

EDGE-TRIGGERED FLIP-FLOP

LOW POWER SCHOTTKY

J SUFFIX

CERAMIC

CASE 632-08

N SUFFIX

PLASTIC

CASE 646-06

14

1

14

1

ORDERING INFORMATION

SN54LSXXJ

Ceramic

SN74LSXXN

Plastic

SN74LSXXD

SOIC

14

1

D SUFFIX

SOIC

CASE 751A-02

LOGIC SYMBOL

14

1

3

12

13

J

Q

CP

K

Q

CD

2

VCC = PIN 4

GND = PIN 11

7

5

10

9

8

J

Q

CP

K

Q

CD

6