Data Sheet

AD5696/AD5694

Rev. A | Page 21 of 24

Instantaneous DAC Updating (LDAC Held Low)

For instantaneous updating of the DACs, LDAC is held low while

data is clocked into the input register using Command 0001. Both

the addressed input register and the DAC register are updated on

Deferred DAC Updating (LDAC Pulsed Low)

For deferred updating of the DACs, LDAC is held high while data

is clocked into the input register using Command 0001. All DAC

outputs are asynchronously updated by pulling LDAC low after the

LDAC MASK REGISTER

Command 0101 is reserved for the software LDAC function.

When this command is executed, the address bits are ignored.

When writing to the DAC using Command 0101, the 4-bit LDAC

mask register (DB3 to DB0) is loaded. Bit DB3 of the LDAC mask

register corresponds to DAC D; Bit DB2 corresponds to DAC C;

Bit DB1 corresponds to DAC B; and Bit DB0 corresponds to

DAC A.

The default value of these bits is 0; that is, the LDAC pin works

normally. Setting any of these bits to 1 forces the selected DAC

channel to ignore transitions on the LDAC pin, regardless of the

state of the hardware LDAC pin. This flexibility is useful in appli-

cations where the user wishes to select which channels respond

to the LDAC pin.

The LDAC mask register allows the user extra flexibility and

control over the hardware LDAC pin (see Table 13). Setting

the LDAC bit (DB3 to DB0) to 0 for a DAC channel allows the

hard-ware LDAC pin to control the updating of that channel.

Table 13. LDAC Overwrite Definition

Load LDAC Register

LDAC Bit

(DB3 to DB0)

LDAC Pin

LDAC Operation

0

1 or 0

Determined by the LDAC pin.

1

X1

DAC channels are updated. (DAC

channels see LDAC pin as 1.)

1

X = don’t care.

HARDWARE RESET PIN (RESET)

RESET is an active low reset that allows the outputs to be cleared

to either zero scale or midscale. The clear code value is user select-

able via the reset select pin (RSTSEL). It is necessary to

keep RESET low for a minimum of 30 ns to complete the

operation.

When the RESET signal is returned high, the output remains at

the cleared value until a new value is programmed. The outputs

cannot be updated with a new value while the RESET pin is low.

There is also a software executable reset function that resets the

DAC to the power-on reset code. Command 0110 is designated

for this software reset function (see Table 8). Any events

on LDAC or RESET during power-on reset are ignored.

RESET SELECT PIN (RSTSEL)

The AD5696/AD5694 contain a power-on reset circuit that

controls the output voltage during power-up. When the RSTSEL

pin is tied to GND, the outputs power up to zero scale (note

that this is outside the linear region of the DAC). When the

The outputs remain powered up at the level set by the RSTSEL

pin until a valid write sequence is made to the DAC.

Table 14. Write Commands and LDAC Pin Truth Table1

Command

Description

Hardware LDAC

Pin State

Input Register

Contents

DAC Register Contents

0001

Write to Input Register n (dependent on LDAC)

Data update

No change (no update)

GND2

Data update

Data update

0010

Update DAC Register n with contents of Input

Register n

No change

Updated with input register

contents

GND

No change

Updated with input register

contents

0011

Write to and update DAC Channel n

Data update

Data update

GND

Data update

Data update

1

A high to low transition on the hardware LDAC pin always updates the contents of the DAC register with the contents of the input register on channels that are not

masked (blocked) by the LDAC mask register.

2

When the LDAC pin is permanently tied low, the LDAC mask bits are ignored.