AD5686 datasheet(19/24 Pages) AD

19 / 24 page

Data Sheet

AD5696/AD5694

Rev. A | Page 19 of 24

READ OPERATION

When reading data back from the AD5696/AD5694, the user

must begin with a start command followed by an address byte

(R/W = 0), after which the DAC acknowledges that it is prepared

to receive data by pulling SDA low. The address byte must be

followed by the command byte, which determines both the read

command that is to follow and the pointer address to read from;

the command byte is also acknowledged by the DAC. The user

configures the channel to read back the contents of one or more

DAC registers and sets the readback command to active using

the command byte.

Following this, the master establishes a repeated start condition,

and the address is resent with R/W = 1. This byte is acknowledged

by the DAC, indicating that it is prepared to transmit data. Two

bytes of data are then read from the DAC, as shown in Figure 38.

A NACK condition from the master, followed by a stop condition,

completes the read sequence. If more than one DAC is selected,

Channel A is read back by default.

MULTIPLE DAC READBACK SEQUENCE

When reading data back from multiple AD5696/AD5694 DACs,

the user begins with an address byte (R/W = 0), after which the

DAC acknowledges that it is prepared to receive data by pulling

SDA low. The address byte must be followed by the command

byte, which is also acknowledged by the DAC. The user selects

the first channel to read back using the command byte.

Following this, the master establishes a repeated start condition,

and the address is resent with R/W = 1. This byte is acknowledged

by the DAC, indicating that it is prepared to transmit data. The

first two bytes of data are then read from DAC Input Register n

(selected using the command byte), most significant byte first, as

shown in Figure 38. The next two bytes read back are the contents

of DAC Input Register n + 1, and the next bytes read back are

the contents of DAC Input Register n + 2. Data is read from the

DAC input registers in this auto-incremented fashion until a

NACK followed by a stop condition follows. If the contents of

DAC Input Register D are read out, the next two bytes of data

that are read are the contents of DAC Input Register A.

Figure 38. I2C Read Operation

FRAME 2

COMMAND BYTE

FRAME 1

SLAVE ADDRESS

R/W

DB23

DB22

DB21

DB20

DB19

DB18

DB17

DB16

START BY

MASTER

ACK BY

AD5696/AD5694

ACK BY

AD5696/AD5694

SCL

SDA

ACK BY

AD5696/AD5694

REPEATED START BY

MASTER

ACK BY

MASTER

FRAME 4

MOST SIGNIFICANT

DATA BYTE n

FRAME 3

SLAVE ADDRESS

ACK BY

MASTER

NACK BY

MASTER

STOP BY

MASTER

FRAME 6

MOST SIGNIFICANT

DATA BYTE n + 1

FRAME 5

LEAST SIGNIFICANT

DATA BYTE n

R/W

DB15

DB14

DB13

DB12

DB11

DB10

DB9

DB8

SDA

SCL

(CONTINUED)

SDA

(CONTINUED)

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

DB15

DB14 DB13 DB12

DB11

DB10

DB9

DB8

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