5-3

FAST AND LS TTL DATA

SN54/74LS174

Symbol

Parameter

Limits

Unit

Test Conditions

Symbol

Parameter

Min

Typ

Max

Unit

Test Conditions

fMAX

Maximum Input Clock Frequency

30

40

MHz

VCC = 5.0 V

CL = 15 pF

tPHL

Propagation Delay, MR to Output

23

35

ns

VCC = 5.0 V

CL = 15 pF

tPLH

tPHL

Propagation Delay, Clock to Output

20

21

30

30

ns

CC = 5.0 V

CL = 15 pF

Symbol

Parameter

Limits

Unit

Test Conditions

Symbol

Parameter

Min

Typ

Max

Unit

Test Conditions

tW

Clock or MR Pulse Width

20

ns

VCC = 5.0 V

ts

Data Setup Time

20

ns

VCC = 5.0 V

th

Data Hold Time

5.0

ns

VCC = 5.0 V

trec

Recovery Time

25

ns

AC WAVEFORMS

Figure 1. Clock to Output Delays, Clock Pulse Width,

Frequency, Setup and Hold Times Data to Clock

Figure 2. Master Reset to Output Delay, Master Reset

Pulse Width, and Master Reset Recovery Time

*The shaded areas indicate when the input is permitted to

1.3 V

1.3 V

1.3 V

1.3 V

1.3 V

1.3 V

1.3 V

1.3 V

1.3 V

1.3 V

1.3 V

1/fmax

tw

ts(H)

th(H)

ts(L)

th(L)

CP

tPHL

tPLH

tW

tPHL

CP

trec

Q

MR

D

Q

*

1.3 V

DEFINITIONS OF TERMS

SETUP TIME (ts) — is defined as the minimum time required

for the correct logic level to be present at the logic input prior to

the clock transition from LOW to HIGH in order to be recog-

nized and transferred to the outputs.

HOLD TIME (th) — is defined as the minimum time following

the clock transition from LOW to HIGH that the logic level must

be maintained at the input in order to ensure continued recog-

nition. A negative HOLD TIME indicates that the correct logic

level may be released prior to the clock transition from LOW to

HIGH and still be recognized.

RECOVERY TIME (trec) — is defined as the minimum time

required between the end of the reset pulse and the clock

transition from LOW to HIGH in order to recognize and transfer

HIGH Data to the Q outputs.