5-1

FAST AND LS TTL DATA

HEX D FLIP-FLOP

The LSTTL / MSI SN54 / 74LS174 is a high speed Hex D Flip-Flop. The

device is used primarily as a 6-bit edge-triggered storage register. The

information on the D inputs is transferred to storage during the LOW to HIGH

clock transition. The device has a Master Reset to simultaneously clear all

flip-flops. The LS174 is fabricated with the Schottky barrier diode process for

high speed and is completely compatible with all Motorola TTL families.

NOTE:

The Flatpak version

has the same pinouts

(Connection Diagram) as

the Dual In-Line Package.

CONNECTION DIAGRAM DIP (TOP VIEW)

14

13

12

11

10

9

1

2

3

4

5

6

7

16

15

8

VCC

MR

Q5

D5

D4

Q4

Q3

D3

CP

Q0

D0

D1

Q1

D2

Q2

GND

PIN NAMES

LOADING (Note a)

HIGH

LOW

D0 – D5

CP

MR

Q0 – Q5

Data Inputs

Clock (Active HIGH Going Edge) Input

Master Reset (Active LOW) Input

Outputs (Note b)

0.5 U.L.

0.5 U.L.

0.5 U.L.

10 U.L.

0.25 U.L.

0.25 U.L.

0.25 U.L.

5 (2.5) U.L.

NOTES:

a. 1 TTL Unit Load (U.L.) = 40

µA HIGH/1.6 mA LOW.

b. The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74)

LOGIC DIAGRAM

D Q

CP

CD

Q5

Q4

Q3

Q2

Q1

Q0

CP

D5

D4

D3

D2

D1

D0

MR

14

2

6

7

3

4

5

9

11

12

10

13

15

D Q

CP

CD

D Q

CP

CD

D Q

CP

CD

D Q

CP

CD

D Q

CP

CD

1

VCC = PIN 16

GND = PIN 8

= PIN NUMBERS

SN54/74LS174

HEX D FLIP-FLOP

LOW POWER SCHOTTKY

J SUFFIX

CERAMIC

CASE 620-09

N SUFFIX

PLASTIC

CASE 648-08

16

1

16

1

ORDERING INFORMATION

SN54LSXXXJ

Ceramic

SN74LSXXXN

Plastic

SN74LSXXXD

SOIC

16

1

D SUFFIX

SOIC

CASE 751B-03

LOGIC SYMBOL

VCC = PIN 16

GND = PIN 8

D5

D4

D3

D2

D1

D0

9

1

3 4 6 11 13 14

CP

MR

Q2

Q1

Q0

Q3 Q4 Q5

2

5 7 10 12 15