FG256 datasheet(49/108 Pages) ACTEL

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SX-A Family FPGAs

v5.3

2-29

Table 2-23 • A54SX16A Timing Characteristics

(Worst-Case Commercial Conditions VCCA = 2.25 V, VCCI = 3.0 V, TJ = 70°C)

Parameter

Description

–3 Speed*

–2 Speed

–1 Speed

Std. Speed

–F Speed

Units

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.

Dedicated (Hardwired) Array Clock Networks

tHCKH

Input Low to High

(Pad to R-cell Input)

1.2

1.4

1.6

1.8

2.8

tHCKL

Input High to Low

(Pad to R-cell Input)

1.0

1.1

1.3

1.5

2.2

tHPWH

Minimum Pulse Width High

1.4

1.7

1.9

2.2

3.0

tHPWL

Minimum Pulse Width Low

1.4

1.7

1.9

2.2

3.0

tHCKSW

Maximum Skew

0.3

0.4

0.6

tHP

Minimum Period

2.8

3.4

3.8

4.4

6.0

fHMAX

Maximum Frequency

357

294

263

227

167

MHz

Routed Array Clock Networks

tRCKH

Input Low to High (Light Load)

(Pad to R-cell Input)

1.0

1.2

1.3

1.5

2.1

tRCKL

Input High to Low (Light Load)

(Pad to R-cell Input)

1.1

1.3

1.5

1.7

2.4

tRCKH

Input Low to High (50% Load)

(Pad to R-cell Input)

1.1

1.3

1.4

1.7

2.3

tRCKL

Input High to Low (50% Load)

(Pad to R-cell Input)

1.1

1.3

1.5

1.7

2.4

tRCKH

Input Low to High (100% Load)

(Pad to R-cell Input)

1.3

1.5

1.7

2.0

2.7

tRCKL

Input High to Low (100% Load)

(Pad to R-cell Input)

1.3

1.5

1.7

2.0

2.8

tRPWH

Minimum Pulse Width High

1.4

1.7

1.9

2.2

3.0

tRPWL

Minimum Pulse Width Low

1.4

1.7

1.9

2.2

3.0

tRCKSW

Maximum Skew (Light Load)

0.8

0.9

1.0

1.2

1.7

tRCKSW

Maximum Skew (50% Load)

0.8

0.9

1.0

1.2

1.7

tRCKSW

Maximum Skew (100% Load)

1.0

1.1

1.3

1.5

2.1

Note: *All –3 speed grades have been discontinued.

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