TS68C429AMFBSLASHC datasheet(21/43 Pages) ATMEL

21 / 43 page

TS68C429A

2120A–HIREL–08/02

Figure 15. Transmitter Channel Unit Outputs

Description

The block diagram of a transmit channel is given is given in Figure 16. Only the third

channel can be switched to internal lines for test mode, otherwise the channels are iden-

tical. The selection of this test mode is done by programming the test bit in the

transmitter-control-register (see “Register Description” on page 17). In this test mode

the lines TX3H and TX3L are not driven, they are both kept at “0”.

The transmit frequency is generated by dividing the ARINC clock signal (CLK ARINC)

by the value contained in the frequency register. This divided clock synchronizes the

shift register which sends the 32-bit word on the lines TXiH and TXiL.

The parity is computed and if requested (see “Register Description” on page 17) the par-

ity bit (32nd bit of the message) is modified to have an odd number of “1” in the 32-bit

message for odd parity or an even number of “1” in the 32-bit message for even parity.

A gap control block generates a gap between the sent messages. The value of this gap

is defined by the 5 bits “transmission gap” of the transmitter-control-register, it is given in

number of ARINC bit (see “Register Description” on page 17).

A FIFO control block manages the messages to be sent. Up to 8 messages can be writ-

ten into the FIFO. The FIFO is seen as a two 16-bit memory words, the Most Significant

Word of the message (MSW) is written in the lower address, the Least Significant Word

of the message (LSW) is written in the upper address. The MSW should be written first.

The access to the FIFO is 16 bits mandatory. The number of messages within the FIFO

is indicated by a counter that can be read through the transmitter-control-register. This

counter is incremented when the LSW is written and decremented when the message is

transferred to the shift-register. The “Reset FIFO” bit is used to cancel messages within

the FIFO. If a transmission is on going, the entire message will be sent. The “reset

FIFO” bit remains active until written at 1 by the microprocessor. When the transmitter is

disable during a transmission, the out going message is lost.

When the FIFO is empty, a bit is set in the status-register (see “General Circuit Control”

on page 24). If the interrupt mode is enabled (see “General Circuit Control” on page 24)

the IRQTX line is activated.

When the transmitter FIFO is empty and when no transmission is on going, the first write

access to the FIFO has to be preceded by the following sequence: disable and enable

transmission (see Figure 36: First FIFO access).

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