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AS8650B датащи(PDF) 34 Page - ams AG

номер детали AS8650B
подробное описание детали  High-efficient Power Management Device with High-speed CAN Interface
PDF  47 Pages
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производитель  AMSCO [ams AG]
домашняя страница  http://www.ams.com
Logo AMSCO - ams AG

AS8650B датащи(HTML) 34 Page - ams AG

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Revision 1.1
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AS8650B
Datasheet - Application In form atio n
8.1.2 SPI Read Operation
The SPI read operation also begins with clock polarity selection at negative edge of CS, given in Table 20. Once the clock polarity is selected the
SPI read command is given by providing ‘1’ in R/W bit of the header field in first sampling edge at SDI pin. The 5 bits address of register to be
read is provided at SDI pin in next five consecutive sampling edges of SCLK. The first 2 bits in header fields are reserved and set to ‘0’. The read
data is followed by last bit of header field on SDO pin. With each sampling edge a bit can be read on SDO pin starting from MSB to LSB. During
complete SPI read operation the CS has to be ‘low’. The SPI read operation ends with positive edge of CS. The wave form for SPI read operation
with single data byte is shown in Figure 18 and Figure 19.
Figure 18. SPI Read Operation with Negative Clock Polarity and 1 Byte of Data Field
Figure 19. SPI Read Operation with Positive Clock Polarity and 1 Byte of Data Field
D7
D6
D5
D4
D3
D2
D1
D0
R1
R0
A4
A3
A2
A1
A0
SCLK
SDI
CS
SDO
Sampling Edge
High Impedance Sate
SCLK
SDI
CS
SDO
R1
R0
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
Sampling Edge
High Impedance Sate



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