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Revision 1.1

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AS8650B

Datasheet - Electrical Character i s t ics

Characteristics of the SDA and SCLK Bus Lines for F/S Mode I²C Bus.

will automatically be the case if the device do not stretch the low period of the SCLK signal. If such a device does stretch the low period

I²C bus specification) before the SCLK line released.

5. This device internally provides a hold time of at least 300ns for the SDA signal to bridge the undefined region of the falling edge of the

SCLK.

Table 15. I²C Timing Parameters

Symbol

Parameter

Standard

Fast

Units

Min

Max

Min

Max

(see Footnote 1)

SCLK clock frequency

0

100

0

400

kHz

Hold time (repeated) START condition.

After this period, the first clock pulse is

generated

4-

0.6

-

µs

Low period of the SCLK clock

4.7

-

1.3

-

µ

s

High period of the SCLK clock

4.0

-

0.6

-

µ

s

Set-up time for a repeated START

condition

4.7

-

0.6

-

µ

s

Data set-up time

250

-

100

(see Footnote 2)

-ns

Data hold-time

0

(see Footnote 5)

3450

(see Footnote 3)

0

(see Footnote 5)

900

(see Footnote 3)

ns

Rise time of SDA and SCLK signals

-

1000

20+

(see Footnote 4)

300

ns

Fall time of SDA and SCLK signals

-

300

20+

(see Footnote 4)

300

ns

Set-up time for STOP condition

4.0

-

0.6

-

µ

s

Bus free time between a STOP and

START condition

4.7

-

1.3

-

µ

s

Capacitive load for each bus line

-

400

-

400

pF

Noise margin at the Low level for each

connected device (including hysteresis)

0.1V*LDO1

-

0.1V*LDO1

-

Noise margin at the High level for each

connected device (including hysteresis)

0.2V*LDO1

-

0.2V*LDO1

-