64GA106 datasheet(214/330 Pages) MICROCHIP

214 / 330 page

PIC24FJ256GA110 FAMILY

DS39905E-page 214

 2010 Microchip Technology Inc.

bit 7-0

CAL<7:0>:

RTC Drift Calibration bits

01111111

= Maximum positive adjustment; adds 508 RTC clock pulses every one minute

...

00000001

= Minimum positive adjustment; adds 4 RTC clock pulses every one minute

00000000

= No adjustment

11111111

= Minimum negative adjustment; subtracts 4 RTC clock pulses every one minute

...

10000000

= Maximum negative adjustment; subtracts 512 RTC clock pulses every one minute

RCFGCAL: RTCC CALIBRATION AND CONFIGURATION REGISTER(1) (CONTINUED)

Note 1:

The RCFGCAL register is only affected by a POR.

A write to the RTCEN bit is only allowed when RTCWREN = 1.

This bit is read-only; it is cleared to ‘0’ on a write to the lower half of the MINSEC register.

PADCFG1: PAD CONFIGURATION CONTROL REGISTER

U-0

—

bit 15

bit 8

U-0

R/W-0

—

RTSECSEL(1)

PMPTTL

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 15-2

Unimplemented:

Read as ‘0’

bit 1

RTSECSEL:

RTCC Seconds Clock Output Select bit(1)

= RTCC seconds clock is selected for the RTCC pin

= RTCC alarm pulse is selected for the RTCC pin

bit 0

PMPTTL:

PMP Module TTL Input Buffer Select bit

= PMP module inputs (PMDx, PMCS1) use TTL input buffers

= PMP module inputs use Schmitt Trigger input buffers

Note 1:

To enable the actual RTCC output, the RTCOE (RCFGCAL<10>) bit must also be set.

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