64GA106 datasheet(212/330 Pages) MICROCHIP

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PIC24FJ256GA110 FAMILY

DS39905E-page 212

 2010 Microchip Technology Inc.

19.1

RTCC Module Registers

The RTCC module registers are organized into three

categories:

• RTCC Control Registers

• RTCC Value Registers

• Alarm Value Registers

19.1.1

To limit the register interface, the RTCC Timer and

Alarm Time registers are accessed through corre-

sponding register pointers. The RTCC Value register

window (RTCVALH and RTCVALL) uses the RTCPTR

bits (RCFGCAL<9:8>) to select the desired Timer

By writing to the RTCVALH byte, the RTCC Pointer

value, RTCPTR<1:0> bits, decrement by one until they

reach ‘00’. Once they reach ‘00’, the MINUTES and

SECONDS value will be accessible through RTCVALH

and RTCVALL until the pointer value is manually

changed.

TABLE 19-1:

RTCVAL REGISTER MAPPING

The Alarm Value register window (ALRMVALH and

ALRMVALL)

uses

the

ALRMPTR

bits

(ALCFGRPT<9:8>) to select the desired Alarm register

pair (see Table 19-2).

By writing to the ALRMVALH byte, the Alarm Pointer

value, ALRMPTR<1:0> bits, decrement by one until

they reach ‘00’. Once they reach ‘00’, the ALRMMIN

and ALRMSEC value will be accessible through

ALRMVALH and ALRMVALL until the pointer value is

manually changed.

TABLE 19-2:

ALRMVAL REGISTER

MAPPING

Considering that the 16-bit core does not distinguish

between 8-bit and 16-bit read operations, the user must

be aware that when reading either the ALRMVALH or

ALRMVALL bytes will decrement the ALRMPTR<1:0>

value. The same applies to the RTCVALH or RTCVALL

bytes with the RTCPTR<1:0> being decremented.

19.1.2

WRITE LOCK

In order to perform a write to any of the RTCC Timer

registers, the RTCWREN bit (RCFGCAL<13>) must be

set (refer to Example 19-1).

EXAMPLE 19-1:

SETTING THE RTCWREN

BIT

RTCPTR

<1:0>

RTCC Value Register Window

RTCVAL<15:8>

RTCVAL<7:0>

MINUTES

SECONDS

WEEKDAY

HOURS

MONTH

DAY

—

YEAR

ALRMPTR

<1:0>

Alarm Value Register Window

ALRMVAL<15:8> ALRMVAL<7:0>

ALRMMIN

ALRMSEC

ALRMWD

ALRMHR

ALRMMNTH

ALRMDAY

——

Note:

This only applies to read operations and

not write operations.

Note:

To avoid accidental writes to the timer, it is

recommended that the RTCWREN bit

(RCFGCAL<13>) is kept clear at any

other time. For the RTCWREN bit to be

set, there is only 1 instruction cycle time

window allowed between the unlock

sequence and the setting of RTCWREN;

therefore, it is recommended that code

follow the procedure in Example 19-1.

For applications written in C, the unlock

sequence should be implemented using

in-line assembly.

asm volatile("disi #5");

__builtin_write_RTCWEN();

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