PIC16F882-I datasheet(210/328 Pages) MICROCHIP

210 / 328 page

PIC16F882/883/884/886/887

DS41291F-page 208

13.4.17

SSP MASK REGISTER

An SSP Mask (SSPMSK) register is available in I2C

Slave mode as a mask for the value held in the

SSPSR

during

address

comparison

operation. A zero (‘0’) bit in the SSPMSK register has

the effect of making the corresponding bit in the

SSPSR register a “don’t care”.

This register is reset to all ‘1’s upon any Reset

condition and, therefore, has no effect on standard

SSP operation until written with a mask value.

This register must be initiated prior to setting

SSPM<3:0> bits to select the I2C Slave mode (7-bit or

10-bit address).

This register can only be accessed when the appropriate

mode is selected by bits (SSPM<3:0> of SSPCON).

The SSP Mask register is active during:

• 7-bit Address mode: address compare of A<7:1>.

• 10-bit Address mode: address compare of A<7:0>

only. The SSP mask has no effect during the

reception of the first (high) byte of the address.

SSPMSK: SSP MASK REGISTER(1)

R/W-1

MSK7

MSK6

MSK5

MSK4

MSK3

MSK2

MSK1

MSK0(2)

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7-1

MSK<7:1>: Mask bits

= The received address bit n is compared to SSPADD<n> to detect I2C address match

= The received address bit n is not used to detect I2C address match

bit 0

MSK<0>: Mask bit for I2C Slave mode, 10-bit Address(2)

I2C Slave mode, 10-bit Address (SSPM<3:0> = 0111):

= The received address bit 0 is compared to SSPADD<0> to detect I2C address match

= The received address bit 0 is not used to detect I2C address match

Note 1: When SSPCON bits SSPM<3:0> = 1001, any reads or writes to the SSPADD SFR address are accessed

through the SSPMSK register.

2: In all other SSP modes, this bit has no effect.

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