DSPIC33FJ64GP706 datasheet(74/322 Pages) MICROCHIP

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dsPIC33FJXXXGPX06/X08/X10

DS70286C-page 72

5.2

RTSP Operation

The dsPIC33FJXXXGPX06/X08/X10 Flash program

memory array is organized into rows of 64 instructions

or 192 bytes. RTSP allows the user to erase a page of

memory, which consists of eight rows (512 instructions)

at a time, and to program one row or one word at a

time. Table 25-12 illustrates typical erase and program-

ming times. The 8-row erase pages and single row

write rows are edge-aligned, from the beginning of pro-

gram memory, on boundaries of 1536 bytes and 192

bytes, respectively.

The program memory implements holding buffers that

can contain 64 instructions of programming data. Prior

to the actual programming operation, the write data

must be loaded into the buffers in sequential order. The

instruction words loaded must always be from a group

of 64 boundary.

The basic sequence for RTSP programming is to set up

a Table Pointer, then do a series of TBLWT instructions

to load the buffers. Programming is performed by

setting the control bits in the NVMCON register. A total

of 64 TBLWTL and TBLWTH instructions are required

to load the instructions.

All of the table write operations are single-word writes

(two instruction cycles) because only the buffers are

written. A programming cycle is required for

programming each row.

5.3

Programming Operations

A complete programming sequence is necessary for

programming or erasing the internal Flash in RTSP

mode.

The

processor

stalls

(waits)

until

the

programming operation is finished.

The programming time depends on the FRC accuracy

(see Table 25-19) and the value of the FRC Oscillator

Tuning register (see Register 9-4). Use the following

formula to calculate the minimum and maximum values

for the Row Write Time, Page Erase Time and Word

Write Cycle Time parameters (see Table 25-12).

EQUATION 5-1:

PROGRAMMING TIME

For example, if the device is operating at +85°C, the

FRC accuracy will be ±2%. If the TUN<5:0> bits (see

Row Write Time is:

and, the Maximum Row Write Time is:

Setting the WR bit (NVMCON<15>) starts the opera-

tion, and the WR bit is automatically cleared when the

operation is finished.

5.4

Control Registers

There are two SFRs used to read and write the

program Flash memory:

• NVMCON: Flash Memory Control Register

• NVMKEY: Non-Volatile Memory Key Register

The NVMCON register (Register 5-1) controls which

blocks are to be erased, which memory type is to be

programmed and the start of the programming cycle.

NVMKEY (Register 5-2) is a write-only register that is

used for write protection. To start a programming or

erase sequence, the user must consecutively write 55h

and AAh to the NVMKEY register. Refer to Section 5.3

“Programming Operations” for further details.

7.37 MHz

FRC Accuracy

()%

FRC Tuning

()%

--------------------------------------------------------------------------------------------------------------------------

TRW

11064 Cycles

7.37 MHz

10.02

()

1 0.00375

–

()

---------------------------------------------------------------------------------------------- 1.48ms

TRW

11064 Cycles

7.37 MHz

10.02

–

()

1 0.00375

–

()

---------------------------------------------------------------------------------------------- 1.54ms

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