DSPIC33FJ64GP706 datasheet(66/322 Pages) MICROCHIP

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dsPIC33FJXXXGPX06/X08/X10

DS70286C-page 64

4.4.3

MODULO ADDRESSING

APPLICABILITY

Modulo Addressing can be applied to the Effective

Address (EA) calculation associated with any W

boundaries check for addresses less than, or greater

than, the upper (for incrementing buffers) and lower (for

decrementing buffers) boundary addresses (not just

equal to). Address changes may, therefore, jump

beyond boundaries and still be adjusted correctly.

4.5

Bit-Reversed Addressing

Bit-Reversed Addressing mode is intended to simplify

data re-ordering for radix-2 FFT algorithms. It is

supported by the X AGU for data writes only.

The modifier, which may be a constant value or register

contents, is regarded as having its bit order reversed. The

address source and destination are kept in normal order.

Thus, the only operand requiring reversal is the modifier.

4.5.1

BIT-REVERSED ADDRESSING

IMPLEMENTATION

Bit-Reversed Addressing mode is enabled when:

BWM bits (W register selection) in the

MODCON register are any value other than ‘15’

(the

stack

cannot

accessed

using

Bit-Reversed Addressing).

The BREN bit is set in the XBREV register.

The addressing mode used is Register Indirect

with Pre-Increment or Post-Increment.

If the length of a bit-reversed buffer is M = 2N bytes,

the last ‘N’ bits of the data buffer start address must

be zeros.

XB<14:0> is the Bit-Reversed Address modifier, or

‘pivot point’, which is typically a constant. In the case of

an FFT computation, its value is equal to half of the FFT

data buffer size.

When enabled, Bit-Reversed Addressing is only

executed for Register Indirect with Pre-Increment or

Post-Increment Addressing and word sized data writes.

It will not function for any other addressing mode or for

byte sized data and normal addresses are generated

instead. When Bit-Reversed Addressing is active, the

W Address Pointer is always added to the address

modifier (XB) and the offset associated with the Regis-

ter Indirect Addressing mode is ignored. In addition, as

word sized data is a requirement, the LSb of the EA is

ignored (and always clear).

If Bit-Reversed Addressing has already been enabled

by setting the BREN (XBREV<15>) bit, then a write to

the XBREV register should not be immediately followed

by an indirect read operation using the W register that

has been designated as the bit-reversed pointer.

Note:

The modulo corrected effective address is

written back to the register only when

Pre-Modify or Post-Modify Addressing

mode is used to compute the effective

address. When an address offset (e.g.,

[W7+W2]) is used, Modulo Address

correction is performed but the contents of

the register remain unchanged.

Note:

All bit-reversed EA calculations assume

word sized data (LSb of every EA is

always clear). The XB value is scaled

accordingly to generate compatible (byte)

addresses.

Note:

Modulo Addressing and Bit-Reversed

Addressing

should

not

enabled

together. In the event that the user attempts

to do so, Bit-Reversed Addressing will

assume priority when active for the X

WAGU and X WAGU Modulo Addressing

will

disabled.

However,

Modulo

Addressing will continue to function in the X

RAGU.

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