CBTL04DP211

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© NXP B.V. 2012. All rights reserved.

Product data sheet

Rev. 2 — 13 April 2012

6 of 18

NXP Semiconductors

CBTL04DP211

DisplayPort 2 : 1 multiplexer

7.

Functional description

Refer to Figure 1 “Functional diagram”.

The CBTL04DP211 uses a 3.3 V power supply. All Main Link signal paths are

implemented using high-bandwidth pass-gate technology and are non-directional. No

clock or reset signal is needed for the multiplexer to function.

The switch position for the main link differential channels and Hot Plug Detect signals is

selected using the select signal GPU_SEL. Additionally, the signal AUX_SEL selects

between two AUX positions. The detailed operation is described in Section 7.1

“Multiplexer/switch select functions”.

7.1 Multiplexer/switch select functions

The internal multiplexer switch position is controlled by two logic inputs GPU_SEL and

AUX_SEL as described below.

Table 3.

Multiplexer/switch select control for IN and OUT channels

GPU_SEL

IN1_n

IN2_n

0

active; connected to OUT_n

high-impedance

1

high-impedance

active; connected to OUT_n

Table 4.

Multiplexer/switch select control for HPD channel

GPU_SEL

HPD_1

HPD_2

0

active; connected to HPD_IN

high-impedance

1

high-impedance

active; connected to HPD_IN

Table 5.

Multiplexer/switch select control for AUX channels

AUX_SEL

AUX1

AUX2

0

active; connected to AUX

high-impedance

1

high-impedance

active; connected to AUX