TPIC44L01, TPIC44L02, TPIC44L03

4CHANNEL SERIAL AND PARALLEL LOW SIDE PREFET DRIVER

12

POST OFFICE BOX 655303

PRINCIPLES OF OPERATION

chipset performance under fault conditions

The TPIC44L01, TPIC44L02, TPIC44L03, and power FET arrays are designed for normal operation over a

battery-voltage range of 8 V to 24 V with load-fault detection from 4.8 V to 34 V. The TPIC44L01, TPIC44L02,

and TPIC44L03 offer onboard fault detection to handle a variety of faults that may occur within a system. The

circuits primary function is to prevent damage to the load and the power FETs in the event that a fault occurs.

reporting of open-load fault conditions. The circuitry detects the fault, shuts off the output to the FET, and reports

the fault to the microcontroller. The primary faults under consideration are:

1.

Shorted load

2.

Open load

3.

Over-battery voltage shutdown

4.

Under-battery voltage shutdown (TPIC44L01 and TPIC44L02 only)

NOTE:

should initialize the fault register after power up to clear any false fault reports.

shorted-load fault condition

The TPIC44L01, TPIC44L02, and TPIC44L03 monitor the drain voltage of each channel to detect shorted-load

conditions. The onboard deglitch timer starts running when the gate output to the power FET transitions from

the off state to the on state. The timer provides a 60-

stabilize after the power FET has been turned on. The deglitch time is only enabled for the first 60

µs after the

FET has been turned on. After the deglitch delay time, the drain voltage is checked to verify that it is less than

the fault reference voltage. When it is greater than the reference voltage for at least the short-to-battery deglitch

off (TPIC44L01 and TPIC44L03) until the error condition has been corrected.

An overheating condition on the FET occurs when the controller continually tries to reenable the output under

shorted-load fault conditions. When a shorted-load fault is detected using the TPIC44L02, the gate output is

transitioned into a low-duty cycle, PWM signal to to protect the FET from overheating. The PWM rate is defined

corrected or until the controller disables the gate output.

The microcontroller can read the serial port on the predriver to isolate which channel reported the fault condition.

Fault bits 0-3 distinguish faults for each of the output channels. When a shorted-load condition occurs with the

TPIC44L01 or TPIC44L03, the controller must disable and reenable the channel to clear the fault register and

FLT. The TPIC44L02 automatically retries the output and the fault clears after the fault condition has been

corrected. Figure 14 illustrates operation after a gate output has been turned on. The gate to the power FET

is turned on and the deglitch timer starts running. Under normal operation T1 turns on and the drain operates

below the reference point set at U1. The output of U1 is low and a fault condition is not flagged.