TPIC44L01 datasheet(7/24 Pages) TI

7 / 24 page

TPIC44L01, TPIC44L02, TPIC44L03

4CHANNEL SERIAL AND PARALLEL LOW SIDE PREFET DRIVER

SLIS062B – NOVEMBER 1996 – REVISED AUGUST 2001

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

switching characteristics, VCC = 5 V, Vbat = 12 V, TC = 25°C

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

t(STBFM)

Short-to-battery/shorted-load/open-load

fault mask time

See Figures 14 and 15

µs

t(STBDG)

Short-to-battery/shorted-load deglitch time

See Figure 14

µs

tPLH

Propagation turnon delay time, CS or

IN0-IN3 to GATE0–GATE3

C(gate) = 400 pF,

See Figure 1

µs

tPHL

Propagation turnoff delay time, CS or

IN0-IN3 to GATE0–GATE3

C(gate) = 400 pF,

See Figure 2

3.5

µs

tr(1)

Rise time GATE0–GATE3

C(gate) = 400 pF,

See Figure 3

3.5

µs

tf(1)

Fall time, GATE0–GATE3

C(gate) = 400 pF,

See Figure 4

µs

f(SCLK)

Serial clock frequency

MHz

trf(SB)

Refresh time, short-to-battery

TPIC46L01 only,

See Figure 14

Refresh pulse width, short-to-battery

TPIC46L01 only,

See Figure 14

µs

tsu(1)

Setup time, CS

↓ to ↑SCLK

See Figure 5

tpd(1)

Propagation delay time, CS

↓ to SDO valid

RL = 10 kΩ,

See Figure 6

CL = 200 pF,

tpd(2)

Propagation delay time, SCLK

↓ to SDO

valid

See Figure 6

tpd(3)

Propagation delay time, CS

↑ to SDO

3-state

RL = 10 kΩ,

See Figure 7

CL = 50 pF,

µs

tr2

Rise time, SDO 3-state to SDO valid

RL = 10 kΩ to GND,

CL = 200 pF,

Over-battery fault,

See Figure 8

tf(2)

Fall time, SDO 3-state to SDO valid

RL = 10 kΩ to VCC,

CL = 200 pF,

No faults,

See Figure 9

tr(3)

Rise time, FLT

RL = 10 kΩ,

See Figure 10

CL = 50 pF,

1.2

µs

tf(3)

Fall time, FLT

RL = 10 kΩ,

See Figure 11

CL = 50 pF,

Figure 1

tPLH

50%

90%

CS or IN0–IN3

GATE0–GATE3

Figure 2

tPHL

50%

10%

GATE0–GATE3

IN0–IN3

Figure 3

90%

10%

tr(1)

GATE0–GATE3

Figure 4

GATE0–GATE3

tf(1)

90%

10%

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