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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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STM8S103F2 датащи(PDF) 86 Page - STMicroelectronics |
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STM8S103F2 датащи(HTML) 86 Page - STMicroelectronics |
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86 / 117 page  Unit Fast mode I 2C(1) Standard mode I 2C Parameter Symbol Max (2) Min (2) Max (2) Min (2) - 0.6 - 4.0 STOP condition setup time tsu(STO) μs - 1.3 - 4.7 STOP to START condition time (bus free) tw(STO:STA) pF 400 - 400 Capacitive load for each bus line Cb (1) f MASTER, must be at least 8 MHz to achieve max fast I 2C speed (400kHz) (2) Data based on standard I2C protocol requirement, not tested in production (3) The maximum hold time of the start condition has only to be met if the interface does not stretch the low time (4) The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the undefined region of the falling edge of SCL Figure 42: Typical application with I 2C bus and timing diagram tf(SDA) tr(SDA) tsu(SDA) th(SDA) tf(SCL) tr(SCL) tw(SCLL) tw(SCLH) th(STA) tsu(STO) tsu(STA) tw(STO:STA) SDA SCL 4.7k Ω SDA SCL 100 Ω 100 Ω 4.7k Ω I2C bus START START STOP REPEATED START STM8S V DD V DD ai17490 1. Measurement points are made at CMOS levels: 0.3 x VDD and 0.7 x VDD. 10-bit ADC characteristics 10.3.10 Subject to general operating conditions for VDD, fMASTER, and TA unless otherwise specified. DocID15441 Rev 9 86/117 STM8S103K3 STM8S103F3 STM8S103F2 Electrical characteristics |
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