THS8083APZP datasheet(53/63 Pages) TI

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A−1

Appendix A

PLL Formulas and Register Settings

If:

F(XTL) = frequency of external crystal or master clock connected to XTL1 input of THS8083A

F(VCO) = frequency of THS8083A−internal VCO

F(DTO) = frequency of THS8083A−internal DTO

F(DTOCLK) = frequency of externally available DTO clock output

F(HS) = frequency of HS input

CLKDIV = clock output divider setting

VCODIV = feedback divider in THS8083A−internal analog PLL loop

TERMCNT = feedback divider in THS8083A−internal digital PLL loop

DTO_INC = DTO increment (when NOM_INC is programmed, DTO_INC is initialized to NOM_INC)

Then:

F(VCO) = F(XTL) x VCODIV

F(DTO) = 32 x F(VCO) / DTO_INC

F(DTOCLK) = F(DTO) / CLKDIV

And, if PLL is locked:

F(DTOCLK) = TERMCNT * F(HS)

Summarizing:

DTO_INC = [32xF(XTL)xVCODIV] / [F(DTOCLK)xCLKDIV]

The formats of DTO_INC and NOM_INC:

Both are 33-bit values consisting of a 6-bit integer and a 27-bit fractional part. So, in hexadecimal notation,

the value is between 00.0000000hex and 3F.7FFFFFFhex. The decimal value of the increment is: <integer

part>.<fractional part interpreted as integer value>x2^(−27). This means, to arrive at the decimal value of

the increment:

Interpret the 6 MSBs as an integer value

Interpret the 27 LSBs expressed as a decimal integer value and multiply this by 2^(−27) to arrive at a

fractional value

Add 1 and 2.

Additional restrictions:

− NOM_INC must be within the range [16,32]. During an unlocked condition of the PLL (e.g., during video

format changes), the user needs to take care that the instantaneous DTO increment does not go outside

this valid range. This can be achieved by monitoring the SYNC_DETECT register bit (for no video input)

and the LOCK pin (for unlock) and disabling the PFD (DISABLE_PFD register bit) when no video input or

unlock is detected. This will keep the DTO operting at the nominal frequency. This update must be done

within a few PFD updates (i.e., within a few video line periods) to avoid the DTO from drifting outside its

valid range. When drifting outside this range, the DTO output might become unstable or absent. Since the

I2C interface requires a valid DTO clock, I2C communication errors will occur (no I2C ACK) when a stable

DTO clock is lost. When this happens, a hardware reset (/RESET pin) will be needed to recover.

− CLKDIV must be chosen for different output clock frequency ranges as shown in register map description

for SEL_CLK.

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